Engineer I - Digital Design
About The Position
Microchip is searching for an Engineer I - Design to be part of the Networking and Connectivity Solutions Business Unit. A candidate placed in this position will be a contributor in the Networking and Connectivity Solutions Design Team, focused on bringing advanced connectivity devices to market, including Ethernet switches & bridges, USB hubs & power delivery, PCIe bridges, serial interfaces (SerDes) and other connectivity interfaces. The successful candidate will be responsible for, but not limited to, the following: • Participating in design, FPGA, DFT, Synthesis and other design activities like micro-architecture and documentation • Integrating IP modules, designing RTL blocks, glue logic, interfacing with verification and emulation teams • Performing development activities such as Formal Verification, Clock Domain Crossing (CDC) analysis, Static Timing Analysis, and low power design • Designing custom digital IPs • Emulation and debug (ASIC and FPGA) of the IP and solution • Develop block level test plan documentation based on datasheets and requirements. • Learning and dynamically applying knowledge of the SoC, protocols and standards
Requirements
- Bachelor’s degree in Electrical or equivalent Engineering with 0+ years of relevant industry experience
- Digital design projects using Verilog/System Verilog
- Proficient in Verilog/System Verilog
- Knowkedge of the ASIC design and/or verification flow
- Strong analytical, communication (written and verbal), and documentation skills
- Excellent problem solving, debugging and organization skills.
- Must be highly motivated and able to work in a collaborative group environment.
Nice To Haves
- Knowledge of Ethernet, USB, and/or PCIe protocols desirable.
Responsibilities
- Participating in design, FPGA, DFT, Synthesis and other design activities like micro-architecture and documentation
- Integrating IP modules, designing RTL blocks, glue logic, interfacing with verification and emulation teams
- Performing development activities such as Formal Verification, Clock Domain Crossing (CDC) analysis, Static Timing Analysis, and low power design
- Designing custom digital IPs
- Emulation and debug (ASIC and FPGA) of the IP and solution
- Develop block level test plan documentation based on datasheets and requirements.
- Learning and dynamically applying knowledge of the SoC, protocols and standards
Benefits
- competitive base pay
- restricted stock units
- quarterly bonus payments
- health benefits that begin day one
- retirement savings plans
- industry leading ESPP program with a 2 year look back feature
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
Number of Employees
5,001-10,000 employees
