Engineer-I (Design)

Microchip • Chandler, AZ

13h

About The Position

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: This position is available to start late spring 2026! Microchip is seeking an ENTRY LEVEL , proactive and motivated engineer to join our team, focusing on Full Chip and Block-level Physical Design projects (from netlist to GDS) for the DSPIC divisions at Microchip. In this role, you will be responsible for all phases of physical design implementation, including physical verification and stream-out processes to external foundries, specifically for low-power, high-performance DSPIC microcontrollers with an emphasis on cost efficiency. This position requires strong technical ownership, advanced problem-solving abilities, and the capability to independently manage complex design and workflow challenges

Requirements

• Bachelor/ master’s degree in one or more of the following disciplines: Electrical/Electronics Engineering, Computer Engineering, Computer Science
• 0-3 years experience
• Deep understanding of CMOS device physics, Ultra-Deep-Sub-Micron effects, Semiconductor process technology and ASIC design and implementation flow
• Strong understanding of STA concepts, including setup/hold timing, clock uncertainties, and constraints.
• Ability to work independently under local project lead or supervisor mentorship.
• Strong debugging, analytical, and problem-solving skills.
• Excellent verbal and written communication skills.
• Strong interpersonal skills and ability to collaborate across global teams.

Nice To Haves

• Hands-on experience with Place & Route tools (Innovus / ICC2) is preferred
• Scripting skills in one or more languages is preferred Perl, TCL, Python, Shell
• Basic understanding of RTL design (Verilog / VHDL)

Responsibilities

• Complete Physical Design implementation including:
• Floor planning
• Power planning
• Sensitive signal planning / routing
• Place & Route
• Clock Tree Synthesis (CTS)
• Timing closure using industry-standard tools such as Cadence Innovus and Synopsys ICC2.
• Drive PPA (Power, Performance, Area) optimization
• Physical verification (DRC/LVS) and IP integration at full chip level.
• Ownership of Physical Design flow and methodology, including continuous improvement.
• Perform and analyze IR drop and EM (Electromigration) checks to ensure design reliability.
• Apply metric-driven design techniques to enable first-pass silicon success.
• Drive flow, methodology development, and automation to improve productivity and quality.
• Collaborate with cross-functional teams including RTL, Synthesis, STA, CAD, and Signoff teams.
• Development of technology setup files for new technologies
• New tool evaluation and research to support back-end flow improvement

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.
• Benefits of working at Microchip

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level