Distinguished Engineer - Memory Subsystem Center of Excellence (CoE), Custom Silicon

Marvell Technology•Santa Clara, CA

10d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Distinguished Engineer, Memory Subsystem CoE is the senior-most technical authority responsible for end‑to‑end technical ownership of memory subsystems across all programs, customers, and SoCs. This role serves as the single technical point of accountability from architecture through post‑silicon validation and customer engagement. The Chief Engineer ensures delivery of platform‑ready, reusable memory subsystems spanning DDR4/DDR5, LPDDR5/5X, and HBM4/HBM4e, aligned to JEDEC standards and long-term product roadmaps. The role partners closely with Architecture, SoC teams, PCIe/Ethernet/Security CoEs, PHY vendors, and customers to ensure quality, predictability, and scalability of memory subsystem delivery. What You Can Expect Own the Memory Subsystem TFM and technical roadmap across current, next‑generation (N+1), and future (N+2) platforms. Act as the final technical authority for architecture, micro‑architecture, RTL, DV, PHY integration, and system validation decisions. Define and maintain reference architectures, configuration models, and integration guidelines for memory subsystems. Drive sign‑off criteria, quality gates, and KPIs across architecture, DV, and validation. Partner with Memory CoE leadership to ensure consistent execution across multiple programs and sites. Guide cross‑functional teams (architecture, RTL, DV, PHY, FW/SW, validation) to deliver reusable, platform‑quality subsystems—not point solutions. Review and resolve cross‑program technical issues and escalations. Serve as the first technical point of contact for customers on memory subsystem architecture, features, and roadmap. Engage with ecosystem partners (JEDEC, IP vendors, PHY providers) on standards adoption, interoperability, and enablement. Support customer engagements, design reviews, and post‑silicon debug when required. Align memory subsystem evolution with SoC, compute, AI, and interconnect roadmaps across the company.

Requirements

10+ years of experience in memory subsystem, SoC, or IP development.
Expertise in DDR4/DDR5, LPDDR5/5X, and/or HBM architectures and system integration.
Background in architecture, RTL, verification, and silicon bring‑up.
Proven track record owning complex subsystems end‑to-end across multiple products.
Experience working directly with customers and external partners.
Strong technical leadership and decision‑making skills in multi‑site environments.

Nice To Haves

Experience defining reusable subsystem platforms or Centers of Excellence.
Familiarity with CHI/AXI‑based SoC fabrics and cross-subsystem interactions.
Prior role as Chief Engineer, Fellow, or equivalent technical authority.

Responsibilities

Own the Memory Subsystem TFM and technical roadmap across current, next‑generation (N+1), and future (N+2) platforms.
Act as the final technical authority for architecture, micro‑architecture, RTL, DV, PHY integration, and system validation decisions.
Define and maintain reference architectures, configuration models, and integration guidelines for memory subsystems.
Drive sign‑off criteria, quality gates, and KPIs across architecture, DV, and validation.
Partner with Memory CoE leadership to ensure consistent execution across multiple programs and sites.
Guide cross‑functional teams (architecture, RTL, DV, PHY, FW/SW, validation) to deliver reusable, platform‑quality subsystems—not point solutions.
Review and resolve cross‑program technical issues and escalations.
Serve as the first technical point of contact for customers on memory subsystem architecture, features, and roadmap.
Engage with ecosystem partners (JEDEC, IP vendors, PHY providers) on standards adoption, interoperability, and enablement.
Support customer engagements, design reviews, and post‑silicon debug when required.
Align memory subsystem evolution with SoC, compute, AI, and interconnect roadmaps across the company.