Director, Engineering

Qualcomm•San Diego, CA

1d•Onsite

About The Position

Headquartered in San Diego, Qualcomm has been inventing technologies for over 40 years, from 5G to artificial intelligence, IoT to automotive and extended reality applications. Qualcomm is inventing the technologies of an intelligently connected future, spearheading research efforts for the next global wireless standard, and collaborating with industry leaders in the wireless value chain. This position is part of an exciting team in the Central Hardware System Group, working on the latest generation of QUALCOMM’s Snapdragon Products. The successful candidate will exhibit strong technical and interpersonal skills for interacting with Hardware and Software engineers. The charter of the CHS DDR SW Systems team is to ensure that the end-product qualifies the defined acceptance criteria for DDR (in terms of stability, meeting Power and performance numbers). The team is looking for a candidate with a strong background in Firmware/Embedded/RTOS concepts, an understanding of HW concepts, and the ability to drive DDR System Level failures. The candidate is expected to be self-driven to quickly get up to speed on various stability aspects of the software and flexible to take-up tasks as per the project needs. The role involves understanding Server SOC Architecture and DDR Subsystem, including LPDDR5X, LPDDR6, DDR5, DDR6 design, and PMIC system architecture. It also requires analyzing system SW crash dumps and identifying the root cause of stability issues (such as memory corruptions, Memory Lock-ups, Bit flips etc.) reported by different SW groups. The candidate will interact with multiple SW & HW teams to understand DDR System Architecture and follow-up on found DDR defects. This position offers exposure to various quality stages from product development to commercial launch and involves guiding the team on server DDR specific tools developed to catch issues in HW and SW.

Requirements

Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 8+ years of System/Package Design/Technology Engineering or related work experience
Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 7+ years of System/Package Design/Technology Engineering or related work experience
PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ year of System/Package Design/Technology Engineering or related work experience

Nice To Haves

15+ years of industry experience in Device drivers
15+ years of industry experience in Embedded software development in C, C++ and/or assembly
15+ years of industry experience in JTAG, logic analyzers and Oscilloscopes for on-chip debugging
Previous experience in platform bring-up (pre-silicon/post-silicon)
Knowledge in scripting languages (e.g., Perl, Python, etc.)
Good understanding of real-time operating systems
Familiarity with boot loader functionality is a plus
Excellent critical thinker with sharp debugging skills
Excellent communication and collaborative skills

Responsibilities

Exhibit strong technical and interpersonal skills for interacting with Hardware and Software engineers
Drive DDR System Level failures
Quickly get up to speed on various stability aspects of the software
Take-up tasks as per the project needs
Understand Server SOC Architecture and DDR Subsystem which includes understanding of LPDDR5X, LPDDR6, DDR5 and DDR6 design and PMIC system architecture
Analyze system SW crash dumps & identify root cause of stability issues (such as memory corruptions, Memory Lock-ups, Bit flips etc.) reported by different SW groups
Interact with multiple SW & HW teams to understand DDR System Architecture & follow-up on the issues for the DDR defects found
Understand and debug system level issues
Guide on the server DDR specific tools developed by the team to catch issues in HW and SW
Interact closely with cross-functional software teams to verify and debug software stability issues and features
Engage with HW and VI team to identify potential HW bugs
Engage in pre-silicon bring-up on simulation/emulation platforms
Participate in silicon-on dock bring-up activities in the lab
Debug issues reported in DDR area
Define and develop test cases to catch DDRSS specific issues