DFT Design Engineer

AMD•Acton, MA

5d•Hybrid

About The Position

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a Design-for-Testability (DFT) Engineer at AMD, you will own the full DFT lifecycle—from specification definition through post-silicon bring-up—to ensure robust and efficient test solutions. You will collaborate closely with Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers, and Program Management to deliver successful and timely project outcomes. THE PERSON: As part of AMD's Strategic Silicon Solutions (S3) Business Unit, you will help bring customer-specific design requirements to life across a wide range of products, including tablets, gaming consoles, servers, and more. You thrive in a collaborative team environment, take ownership of tasks through to completion, and communicate effectively both verbally and in writing.

Requirements

Strong understanding of Design For Test methodologies and DFT verification (e.g., IEEE1500, JTAG 1149.x, scan, memory BIST).
Experience with Tessent TestKompress and Silicon Scan Network (SSN).
Proficiency with VCS simulation tools, Perl/Shell scripting, and Verilog RTL design.
Exposure to static timing analysis and timing closure processes.
Experience in pre-silicon test planning, validation, and engagement with design teams.
Skilled in characterization and debugging of scan/ATPG tests in new silicon designs and process technologies.
Expertise in optimizing test flows for quality enhancement and cost reduction.
Ability to analyze part failures to improve test coverage and yield.
Experience analyzing characterization data across process, voltage, and temperature (PVT) corners.
Excellent communication skills and ability to work effectively in a global team environment.

Nice To Haves

Knowledge of low power design concepts such as clock gating and power gating is a plus.

Responsibilities

Implement and verify DFT and Design-for-Debug (DFD) architectures and features.
Insert Scan, JTAG, and Boundary Scan chains; generate ATPG patterns.
Generate, implement, and verify Memory Built-In Self-Test (BIST) logic.
Apply low power DFT techniques to designs.
Achieve DFT timing closure and verify ATPG patterns through gate-level simulation with timing.
Analyze test coverage and work on reducing test costs.
Provide post-silicon support to ensure successful bring-up and improve yield learning.