DFT Staff Engineer

Advanced Micro Devices, Inc • Santa Clara, CA

2d • Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

As a member of the Cores DFT Team, the successful candidate will own the ATPG responsibilities for the next generation of AMD high-performance cores.
You will need to factor many multi-dimensional issues such as power, area and timing. Our work is a key contributor to delivering a high-quality design and can improve AMD’s operating expenses in the millions. As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

Requirements

• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
• Experience in debugging low coverage and DRC fixes
• Proficient in logic design using Verilog
• Experience in debugging test pattern issues
• Support of Silicon bringup activities
• Experience with post-silicon debug
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc.
• Experience with Tessent Scan/ATPG
• Excellent presentation and inter-communication skills
• Bachelor's in Electrical Engineering/Computer Engineering

Nice To Haves

• Hands-on expertise with commercial test generation tools for large complex designs
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST
• Experience running test compression software
• Strong sense of ownership
• Self-driven
• Master's degree in Electrical Engineering/Computer Engineering

Responsibilities

• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
• Experience in debugging low coverage and DRC fixes
• Proficient in logic design using Verilog
• Experience in debugging test pattern issues
• Support of Silicon bringup activities
• Experience with post-silicon debug
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc.
• Experience with Tessent Scan/ATPG
• Excellent presentation and inter-communication skills

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees