Design Verification Engineer

Apple•Waltham, MA

5h•Onsite

About The Position

At Apple, the Design Verification Engineer will contribute to crafting products that enrich people's lives by solving complex challenges. This role offers a unique opportunity to shape upcoming products that will inspire millions of customers. The DV engineer will be instrumental in producing fully functional first silicon for IP designs, encompassing all phases of pre-silicon verification. This includes establishing DV methodology, developing test-plans and verification environments (with stimulus and checkers), test-writing, debugging, coverage analysis, and sign-off for RTL freeze and tape-out. The engineer will be responsible for ensuring bug-free first silicon for SoC/IP components, developing detailed test and coverage plans based on micro-architecture, and creating scalable and portable verification methodologies and environments. A mindset to identify design flaws is highly valued. The role also involves developing and implementing verification plans, including design and DV environment bring-up, regression enabling, and debugging test failures. Furthermore, the engineer will develop block, IP, and SoC level test-benches, track and report DV progress using metrics like bugs and coverage, and leverage LLM and related technologies for efficiency and quality.

Requirements

Minimum requirement of a bachelors degree
BS degree in technical subject area and a minimum 3 years relevant industry experience
Strong knowledge of OOP, SystemVerilog and UVM
Strong knowledge in developing scalable and portable test-benches
Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
Some working experience using LLMs for efficiency and quality
Experience with power-aware (UPF) or similar verification methodology
Knowledge of one of the scripting languages such as Python, Perl, TCL

Nice To Haves

Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
Knowledge of formal verification methodology
Knowledge of emulation for verification technologies

Responsibilities

Establish DV methodology
Develop test-plans
Develop verification environment including stimulus and checkers
Perform test-writing
Debug issues
Perform coverage analysis
Sign-off for RTL freeze and tape-out
Ensure bug-free first silicon for part of the SoC / IP
Develop detailed test and coverage plans based on the micro-architecture
Develop verification methodology suitable for the IP, ensuring a scalable and portable environment
Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage
Develop verification plans for all features under your care
Implement verification plans, including design bring-up, DV environment bring-up, regression enabling all features under your care, and debug of the test failures
Develop block, IP and SoC level test-benches
Track and report DV progress using a variety of metrics, including bugs and coverage
Make use of LLM and related technologies to achieve efficient execution and improved quality