Design Verification Engineer

Solidigm • Rancho Cordova, CA

1d

About The Position

Component Design Engineers are responsible for the design and development of electronic components. Responsibilities may include: the design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components, performing developmental and/or test work, reviewing product requirements and logic diagrams, planning and organizing design projects or phases of design projects. Responds to customer/client requests or events as they occur. Develops solutions to problems utilizing formal education and judgement. Key responsibilities Create/update test plan based on design specification and create UVM based direct/constrained-random tests. Debug the simulation and quickly identify design or test issues. Define functional coverage and perform coverage analysis Create/update the SVAs (system-verilog assertions) for 3D NAND design based on verification requirements UVM based verification environment updates. Mixed-signal fullchip modeling includes analog behavioral modeling, cell-level testbench, fullchip level mixed-signal netlist and testbench. Develop scripts to automate the verification flow and data-collections.

Requirements

• Master’s degree with 3+ years experiences or bachelor degree with 5+ years experiences in electrical engineering, Computer Engineering, Computer Science
• Prior experience in memory product pre-silicon verification
• Working experience in UVM, system Verilog assertions, Formal Property Verification
• In-depth knowledge of mixed-signal verification and working experience in mixed-signal design modeling and simulation
• Fundamental digital and analog circuit design knowledge.
• Solid data analysis capability, communication and presentation skills
• Strong independent debugging and problem-solving skills
• Excellent written and verbal communication skills

Responsibilities

• Create/update test plan based on design specification and create UVM based direct/constrained-random tests.
• Debug the simulation and quickly identify design or test issues.
• Define functional coverage and perform coverage analysis
• Create/update the SVAs (system-verilog assertions) for 3D NAND design based on verification requirements
• UVM based verification environment updates.
• Mixed-signal fullchip modeling includes analog behavioral modeling, cell-level testbench, fullchip level mixed-signal netlist and testbench.
• Develop scripts to automate the verification flow and data-collections.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 101-250 employees