Design Verification Engineer

Marvell Technology•Westborough, MA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M® product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc. What You Can Expect In this role, the successful candidate will: · Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers. · Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete. · Develop tests and tune the environment to achieve coverage goals. · Debug failures and work with designers to resolve issues. Other Skills: · Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision. · Requires the ability to accept and work with differing opinions · Must be able to learn on the fly and work in a fast-paced environment.

Requirements

Proficiency using C/C++
Experience with Verilog and SystemVerilog, preferably with UVM.
Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
Experience with scripting language such as Python or Perl and EDA Verification tools.
A good understanding of Linux OS.
BS or MS is Computer Engineering, Electrical Engineering, or Computer Science with 3+ years of verification and firmware and software development experience.
Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
Requires the ability to accept and work with differing opinions
Must be able to learn on the fly and work in a fast-paced environment.

Responsibilities

Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers.
Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete.
Develop tests and tune the environment to achieve coverage goals.
Debug failures and work with designers to resolve issues.