Engineer, Design Verification Engineering

Analog Devices • Chandler, AZ

1d

About The Position

The Digital Mixed Signal (DMS) Verification Team seeking a motivated, Design Verification Engineer to provide support to our Industrial Power Group located at ADI’s Chandler, AZ Design Center. The candidate will verify integrated circuits and support assigned products through the full product life cycle. Emphasis will be mainly on verification, though design assignments will also be available on an as-needed basis.

Requirements

• Bacherlor’s Degree in Electrical or Computer Engineering
• Analog Microelectronics and Digital Systems Design
• SystemVerilog
• Strong written and verbal communication skills
• Strong general coding, object-oriented programming, and documentation skills
• Experience with a scripting language (Perl, Python, C, etc.)

Nice To Haves

• System Verilog Assertion for Dynamic and Formal Verification.
• Fundamental understanding of Universal Verification Methodology
• Working experience with custom digital interfaces (I2C, SPI, UART, etc.)
• Knowledge of linear regulators and switching regulators

Responsibilities

• Verification of state machines, and controlling logic required to implement new products in a wide range of application spaces
• Development of directed and constrained random test cases in SystemVerilog
• Implementation of metric-driven SystemVerilog and UVM verification environments as determined by project complexity
• Mixed Signal Simulation
• Modeling of analog blocks (electrical and real number)

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level