Design Verification Engineer

Broadcom•San Jose, CA

About The Position

The CSG group at Broadcom develops cutting-edge networking ASICs and multichip solutions, specifically Tomahawk ASICs for Scale-Out and Scale-Up AI Networks. These products are highly complex, supporting the latest networking protocols and features, and are designed to manage extremely large volumes of traffic, reaching hundreds of Terabits/sec. They also support a wide range of port speeds from 10/100Mb/s to 1600Gb/s, along with various line interfaces and protocols. The successful candidate for this role will be instrumental in the verification of these advanced network switch routing designs.

Requirements

MSEE or BSEE or equivalent, with concentration in digital design and excellent academic standing
Total engineering minimum experience required is typically a BS degree and 8+ years of experience, an MS degree and 6+ years of experience or a PhD and 3+ years of experience or equivalent
Familiar with Hardware description languages (Verilog/SystemVerilog/UVM), scripting languages (Perl, Python) and Object Oriented Programming (OOP)
Exposure to cutting edge verification and validation techniques and methodologies using Object Oriented modular reusable environments in languages such as Systemverilog, Perl, Python
Strong understanding and prior experience of end-to-end verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production
Excellent verbal and written communication skills

Responsibilities

Participating in the verification processes of L2/L3 Network Switching and routing ASICs and various subsystems within these chips
Understanding the architecture and implementation of these chips and coming up with in-depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems
Developing verification environments including testbenches and verification API’s associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains
Implementing test plans into executable test suites using a cutting edge Systemverilog verification environment
Executing the verification process to completion pre-silicon using various functional and code coverage metrics as measures of completion