Design Verification Engineer IV
About The Position
This position is responsible for architecting Verification Environments for ASIC SoC and providing verification support from defining verification plans to multi-million gate product tapeout, as well as for Test design and development. The role involves developing complex self-checking test benches with constraint random stimulus generation, architecting SoC test FW, and creating test plan documentation to cover ASIC features. The engineer will also develop and debug SoC ASIC platform test FW and specific tests in C/C++. A key aspect of the role is partnering in methodology development activities and actively planning, analyzing, and reviewing functional and technical specification documents. The position requires implementing and maintaining an integrated end-to-end formal verification flow for formal verification objectives, developing/modifying scripts to automate the verification process, and developing verification environments including environment assumptions, assertions, and cover properties in the context of the verification plan. The role requires in-depth knowledge and experience, solving complex problems, and taking new perspectives using existing solutions. The individual works independently, receives minimal guidance, and acts as a resource for colleagues with less experience. This level represents where a career may stabilize for many years or even until retirement. The engineer uses best practices and knowledge of internal or external business issues to improve products/services or processes, typically resolves complex problems or problems where precedent may not exist, often leads the work of project teams, and may formally train junior staff.
Requirements
- Minimum of 8 years of related experience with a 4 year degree; or 6 years and an advanced degree; or equivalent experience
- In-depth knowledge and experience
- Ability to solve complex problems
- Ability to work independently
- Ability to act as a resource for colleagues with less experience
- Ability to use best practices and knowledge of internal or external business issues to improve products/services or processes
Responsibilities
- Architect Verification Environment for ASIC SoC and provide verification support from defining verification plan to multi-million gate product tapeout & for Test design and development
- Develop complex self checking test benches with constraint random stimulus generation
- Architect SoC test FW and create test plan documentation to cover ASIC features
- Develop and debug SoC ASIC platform test FW and specific tests in C/C++
- Partner in methodology development activities & actively plan, analyze and review functional and technical specification documents
- Implement and maintain integrated end-to-end formal verification flow for the formal verification objective
- Develop/modify scripts to automate the verification process
- Develop verification environment including environment assumptions, assertions, and cover properties in context of the verification plan
- Solve complex problems; take a new perspective using existing solutions
- Work independently; receive minimal guidance
- Act as a resource for colleagues with less experience
- Use best practices and knowledge of internal or external business issues to improve products/services or processes
- Resolve complex problems or problems where precedent may not exist
- Lead the work of project teams; may formally train junior staff
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Number of Employees
5,001-10,000 employees
