Design/DFT Physical Design Integration Lead

Altera • San Jose, CA

3d • Onsite

About The Position

About Altera Accelerating Innovators — Altera provides leadership in programmable solutions that are easy to use and deploy across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system‑on‑modules, SmartNICs, and IPUs, offering the flexibility to accelerate innovation. Our innovation in programmable logic began in 1983. Since then, we’ve delivered the tools and technologies that empower customers to innovate, differentiate, and succeed in their markets. Join us on our journey to becoming the world’s #1 FPGA company! Why Join Altera? At Altera, you’ll be part of a team that’s redefining programmable logic and accelerating innovation across industries. We offer a dynamic work environment, cutting‑edge technology, and opportunities to grow your career while shaping the future of compute. About the Role Altera is seeking a Design/DFT Physical Design Integration Lead to join our SoC Physical Design Team!

Requirements

• BS/MS or PhD in Electrical Engineering, Computer Engineering, or a related field and 10+ years of experience in the following:
• Experience in physical design implementation and flow development.
• Experience in Design Constraint (SDC) development, validation, and execution.
• Experience in ATPG implementation/validation, including constraints, implementations, validations, and clocking.
• Industry‑standard EDA tools (Synopsys, Cadence, Siemens).
• Scripting in Tcl, Python, Perl, and Shell.
• Full‑chip implementation and tape‑out of complex SoCs or FPGAs.
• Tming, power, signal integrity, and physical verification.

Nice To Haves

• Hands‑on experience with full ATPG/DFT turnkey flow beyond general PD domain (SDC generation, pre‑layout, RTL verification, post‑layout simulation, ATPG generation, post‑silicon ATPG bring‑up).
• Experience with hierarchical design methodologies and physical IP integration.
• Familiarity with advanced process nodes.
• Knowledge of machine learning techniques applied to EDA flows is a plus.
• Prior experience in FPGA architecture or design is highly desirable.

Responsibilities

• Own and drive design integration tasks focusing on Design/DFT constraint integration.
• Own and drive full‑chip implementation from RTL to GDSII, including timing closure, power optimization, and physical verification.
• Collaborate with RTL, DFT, STA, and packaging teams to ensure seamless integration and convergence across domains.
• Develop and maintain automation scripts (Tcl, Python, Perl, etc.) to enhance productivity and flow robustness.
• Evaluate and integrate EDA tools and methodologies to improve design efficiency and QoR.
• Lead technical reviews and provide guidance to design teams on best practices and flow usage.
• Analyze design metrics and debug complex issues across the physical design flow.
• Drive innovation in physical design methodologies to meet aggressive PPA and schedule targets.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level