GPU Physical Design Engineer Lead

Intel • Folsom, CA

1d • Hybrid

About The Position

The primary responsibilities for this role will include, but are not limited to: In this position, the candidate will be part of a team implementing ASIC designs for Integrated/Discrete Graphics and AI SoCs on leading edge process technology and EDA tools. The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc. Responsibilities may also include defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures. The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle. A successful candidate will have proven experience demonstrating the following skills and behavioral traits: The ideal candidate will be capable of leading a small team as well as interacting with architecture and design teams to improve IP and ultimate product quality and performance. Good leadership and communication skills are necessary due to the nature of the work, size and complexity of the products and the size of the team.

Requirements

• Bachelor’s in Electrical/Computer Engineering with 9+ years relevant work experience, or Master's in Electrical/Computer Engineering with 6+ years relevant work experience.
• Experience in: Logic Design, VLSI/ASIC Design, Computer Architecture.
• Current Industry Experience in one or more ASIC style design flows – floorplanning, clock construction, synthesis, place and route, static timing analysis, layout verification.
• Experience with Unix/Linux, Perl and TCL in order to implement useable, flexible cshell/perl/tcl programs that automate tool/flow methodologies.
• Good leadership and communication skills

Nice To Haves

• Experience in SoC integration methodologies including floorplan/timing integration of a variety of blocks into an SoC design.
• Knowledge of Clock Construction Methodology and Power estimation/optimization.

Responsibilities

• Implementing ASIC designs for Integrated/Discrete Graphics and AI SoCs on leading edge process technology and EDA tools.
• SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc.
• Defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures.
• Work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle.
• Leading a small team
• Interacting with architecture and design teams to improve IP and ultimate product quality and performance.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level