Chip Package Signal and Power Integrity Lead Engineer

Google • Sunnyvale, CA

6d

About The Position

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Chip Package SI/PI Engineer on the implementation team, you will drive package design with signal/power integrity simulation and characterization at the chip, package, and system levels. Within a concurrent engineering environment, you will collaborate with system architects, ASIC engineers, and other SI/PI peers. You will work with cross-functional teams—including chip, board, and system design—as well as vendors to meet all electrical requirements. Our computational challenges are so unique we must build the hardware ourselves. We design the hardware, software, and networking technologies powering all Google services. As a Hardware Engineer, you design systems at the core of the world's most powerful computing infrastructure. You will see those systems from concept through to high-volume manufacturing. Your work has the potential to shape the machinery in our cutting-edge data centers, affecting millions of Google users. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with SI/PI design for chip/package or system PCB.
• Experience in industry SIPI modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).

Nice To Haves

• Master’s degree or PhD in Electrical Engineering or Signal/Power Integrity.
• Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, including expertise in SI/PI analysis for high-speed interconnects (HBMx, D2D, Ethernet, PCIe).
• Knowledge of next-generation memory and chiplet standards, including timing budget and design & sign-off methodologies.
• Understanding of STA, on-chip DVD/EMIR, system voltage budgets, and VR (voltage regulator) modeling and design.
• Excellent cross-functional leadership skills.
• Proficient in Python, Matlab, or C++ to establish automation flows and conduct advanced data processing and analysis.

Responsibilities

• Drive chip-package-system co-design for HPC by performing SI/PI analysis and optimization using 2.5D/3D technologies to refine product definitions, chip floorplans, and power tree structures.
• Develop power integrity methodologies and evaluate new package technologies to enhance accuracy, productivity, and performance for advanced hardware projects.
• Collaborate with chip, system, and supply teams to define SI/PI design targets and explore tradeoffs between performance and DFM for successful production closure.
• Evaluate high-speed interface IP and provide critical feedback on chip floorplans to ensure optimal package/system routability and signal integrity.
• Lead the development of innovative methodologies for advanced package technologies, ensuring smooth implementation from early planning through high-volume manufacturing and failure debug.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees