Automotive HW Methodology Principal Engineer

Qualcomm•San Diego, CA

About The Position

Define and drive end‑to‑end Predictive Maintenance solutions for automotive SoCs, spanning hardware architecture, DFT infrastructure, software enablement, and silicon reliability. The role requires strong SoC architecture experience and a deep understanding of the silicon development lifecycle, from early architecture definition through implementation, validation, qualification, and production. The position works across multiple domains and teams to ensure Predictive Maintenance capabilities are architected, implemented, and productized as part of automotive SoC platforms.

Requirements

Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Requires verbal and written communication skills to convey highly complex and/or detailed information. May require strong negotiation and influence with large groups or high-level constituents.
Has a great degree of influence over key organizational decisions (e.g., is making or directly making key decisions that will have substantial impact over the organization).
Tasks often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively.

Nice To Haves

Strong SoC architecture experience with a solid understanding of the full silicon development lifecycle (architecture definition through production).
Broad cross‑domain knowledge spanning hardware design, DFT/test infrastructure, firmware/software interaction, and system‑level reliability.
Experience with DFT technologies such as MBIST, ATPG, LBIST, in‑system test, and structural test reuse.
Good understanding of silicon aging, reliability mechanisms, and automotive qualification expectations (e.g., lifetime, availability, AEC‑Q100).
Understanding of AI/ML models and data analysis techniques.
Proven ability to drive cross‑functional technical solutions in complex, matrixed engineering organizations.
Automotive or other safety‑critical SoC experience is highly desirable.

Responsibilities

Architect and own Predictive Maintenance solutions across hardware, DFT, software, and reliability domains for automotive SoCs.
Drive SoC‑level architecture decisions to enable silicon health monitoring, aging prediction, and proactive failure mitigation.
Collaborate closely with SoC architecture, DFT, reliability, manufacturing, technology, and software teams throughout the full silicon development cycle (architecture, design, validation, qualification, and production).
Translate reliability and safety requirements into concrete hardware, DFT, and software mechanisms.
Influence methodology, infrastructure, and roadmap decisions to ensure scalable and reusable Predictive Maintenance solutions across automotive programs.
Collaborate with academic partners to explore and develop future models and data analysis techniques.
Represent Predictive Maintenance and silicon health topics in architecture reviews, safety reviews, and cross‑functional technical forums.
Leverages expert ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
Creates highly advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
Collaborates with high-level representatives across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.
Serves as an expert resource for all aspects of the process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC Packages; provides technical expertise and support to team members.
Writes detailed technical documentation for highly complex EDA/IP/ASIC projects; reviews technical documentation for experienced engineers.