ASIC DTCO, Timing and Technology Engineer

Qualcomm•San Diego, CA

1d•$140,000 - $210,000

About The Position

As a DTCO and Timing Engineer, you will play a vital role in DTCO analysis targeting the Mobile, Compute, Automotive and IOT markets. The candidate will work with best-in-class methodologies, tools and implementation flows/technologies to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level in advanced process technologies 5nm, 4nm … 2nm and beyond (process technologies). Responsible for Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre) for power and performance validation and STA sign off using PT/PT-SI and Tempus. The candidate will be responsible for block level PPA analysis/implementation (RTL to GDS flow) for hard macros using FC Synthesis, FC Place and Route, Genus and Innovus. The candidate will be responsible for design implementation of multiple blocks working with foundry DTCO team, EDA companies (partners), CAD team and IP team driving Fmax optimization, PPAY and cost improvements/reduction. You should have good execution knowledge. Your contribution should improve design convergence process across the company, design PPAY and support new advanced process technologies bring-up in production from pdk to vlsi design.

Requirements

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Good execution knowledge.
Good programming skills Python, Perl, TCL, Unix shell, C/C++.

Nice To Haves

ML modeling experience is a plus

Responsibilities

Play a vital role in DTCO analysis targeting the Mobile, Compute, Automotive and IOT markets.
Work with best-in-class methodologies, tools and implementation flows/technologies to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level in advanced process technologies 5nm, 4nm … 2nm and beyond.
Responsible for Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre) for power and performance validation and STA sign off using PT/PT-SI and Tempus.
Responsible for block level PPA analysis/implementation (RTL to GDS flow) for hard macros using FC Synthesis, FC Place and Route, Genus and Innovus.
Responsible for design implementation of multiple blocks working with foundry DTCO team, EDA companies (partners), CAD team and IP team driving Fmax optimization, PPAY and cost improvements/reduction.
Improve design convergence process across the company, design PPAY and support new advanced process technologies bring-up in production from pdk to vlsi design.