ASIC DTCO, Timing and Technology Engineer

Qualcomm • San Diego, CA

3d

About The Position

As a DTCO and Timing Engineer at Qualcomm Technologies, Inc., you will be a crucial part of DTCO analysis for Mobile, Compute, Automotive, and IOT markets. This role involves utilizing advanced methodologies, tools, and implementation flows/technologies to assess process technology entitlement (PPAY) for SOC products at both block/IP-level and system-level, specifically in advanced process technologies like 5nm, 4nm, 2nm, and beyond. You will be responsible for Spice simulations for power and performance validation, as well as STA sign-off. The position also entails block-level PPA analysis and implementation through the RTL to GDS flow for hard macros. You will collaborate with foundry DTCO teams, EDA partners, CAD teams, and IP teams to optimize Fmax, improve PPAY, and reduce costs. A strong execution knowledge is expected, and your contributions will be vital in enhancing the design convergence process, improving design PPAY, and supporting the bring-up of new advanced process technologies in production, from PDK to VLSI design.

Requirements

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Good execution knowledge.
• Good programming skills Python, Perl, TCL, Unix shell, C/C++.

Nice To Haves

• ML modeling experience

Responsibilities

• Play a vital role in DTCO analysis targeting the Mobile, Compute, Automotive and IOT markets.
• Work with best-in-class methodologies, tools and implementation flows/technologies to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level in advanced process technologies 5nm, 4nm … 2nm and beyond.
• Responsible for Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre) for power and performance validation and STA sign off using PT/PT-SI and Tempus.
• Responsible for block level PPA analysis/implementation (RTL to GDS flow) for hard macros using FC Synthesis, FC Place and Route, Genus and Innovus.
• Responsible for design implementation of multiple blocks working with foundry DTCO team, EDA companies (partners), CAD team and IP team driving Fmax optimization, PPAY and cost improvements/reduction.
• Improve design convergence process across the company, design PPAY and support new advanced process technologies bring-up in production from pdk to vlsi design.

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees