FE Design and Timing Engineer

Apple • San Diego, CA

2d

About The Position

In this role you will work on a small team dedicated to implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. There will be the opportunity to work closely with multi-disciplinary groups to meet power, performance, and area goals for Apple’s products. You will interact with RTL designers to understand design intent and clock structure, with CAD to understand and develop flows, with UPF and DFT teams to insert power and test structures, and with Physical design team to close and sign-off timing. Collaboration will be needed to make sure designs are delivered on time and with the highest quality by incorporating targeted checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact in getting leading-edge products launched to delight millions of customers.

Requirements

• Minimum requirements of bachelor's degree.

Nice To Haves

• Knowledge of the ASIC design flow, synthesis, static timing analysis, RTL to Post Synthesis netlist.
• Exposure to industry standard Timing, Logic Equivalence, Physical Design and Synthesis tools.
• Proficient in scripting in TCL, Perl or Python.
• Knowledge of basic SoC Architecture and HDL languages like Verilog / System Verilog to collaborate with our logic design team for timing fixes and functional ECOs.
• Hands-on experience in timing/SDC constraints generation, analysis, and management.
• Knowledge of timing corners, operating conditions, process variations, and signal integrity-related issues.
• Knowledge of Place and Route steps including floor planning, CTS, Routing and timing ECOs.
• Understanding of UPF and low-power design and implementation techniques.
• Understanding of DFT methodologies including Scan and BIST.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees