In this position, the candidate will be part of a team implementing Integrated/Discrete Graphics blocks and AI SoCs on leading edge process technologies and EDA tools. The team is responsible for all SoC level physical design and optimization flows ranging from Floor planning, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN aspects, Layout Verification, etc. The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle. Good interpersonal/communication skills are necessary due to the nature of work, size/complexity of products and the size of the team.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees