Wafer Fabrication Defect Reduction and Yield Enhancement Lead

Google•Fremont, CA

3d•$221,000 - $311,000

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets. The US base salary range for this full-time position is $221,000-$311,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
10 years of experience in semiconductor manufacturing engineering roles.
5 years of experience in technical leadership.
Experience with yield analysis.
Experience with advanced quality tools: statistical process control, design of experiments, Six Sigma, or failure analysis techniques.
Experience with quality control.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).
Experience applying manufacturing statistics and Design of Experiments (DOE), with expert-level proficiency in statistical software (e.g., JMP and Minitab).
Knowledge of semiconductor manufacturing processes, including wafer fabrication (foundry) or assembly, test, and packaging operations, equipment, and material flow.
Knowledge of simple database structures.

Responsibilities

Identify flaws and issues with hardware components.
Analyze and solve key issues, risks, or trade-offs; address ambiguous or new hardware failures by driving corrective solutions.
Evaluate hardware design feasibility based on product requirements.
Identify and customize the design solution based on trade-offs in packaging, performance, power, or technology selection, and scope hardware projects.
Develop and drive the roadmap in collaboration with internal partners and external vendors.
Review and approve activities in a discipline of hardware design, architecture, technology, or development across multiple products or systems.
Review and approve integration of new hardware technologies into product tiers during feature planning.
Advocate for hardware discipline design priorities and help adjudicate between performing product-design priorities.
Compare hardware performance issues across multiple products to ensure consistent delivered quality.
Lead design and process improvement efforts.