Team Lead - FPGA Development (Job Req #2025-314)

Ross Video

About The Position

We are seeking an FPGA Team Lead to join the Graphite Switcher team. Our group is responsible for implementing standalone Linux embedded and PC based Windows/Linux based products. The ideal candidate is a senior developer with the ability to define chip level features and technical requirements and then implement the optimal methodology for the team to deliver the design. This role offers the opportunity to join a team developing platforms which integrate a myriad of different video, audio and transport technologies for world-class media production solutions. In conjunction with FPGA architects, system architects, Marketing and Product managers, the Team Lead will develop and maintain high-level and detail design specifications. They will work with FPGA developers to design, write, edit, and test FPGA coding as per specifications or guidelines, and oversee the development of FPGA design specifications in collaboration with product managers, software design team, and hardware design team. The position involves directing and coordinating FPGA staff, including task scheduling, work verification, and progress monitoring. The Team Lead will also advise and make recommendations to management on FPGA development matters, such as toolset selection, methodologies, and design guidelines, to aid decision-making and planning. Responsibilities also include assisting the manager in prioritizing bugs, managing load building and releasing for all projects, scheduling code inspections, supporting Hardware and Project Managers, and training other staff members.

Requirements

Senior level FPGA design knowledge and experience including: System architecture (Resets, clock domains, flow control, processing, arbitration, etc.), FPGA building blocks (High speed transceivers, DDR4/5 interfaces, PLL’s, PCIe, etc.), Design Implementation (Tool design flows, place and route optimization, timing closure, etc.).
Current AMD (Xilinx) and Altera (Intel) devices and associated design and debugging tools.
Strong Verilog and System Verilog coding and verification skills.
A familiarity with C, C++ and other design languages.
Above average, Windows and Linux computer skills.
Post-secondary degree in Engineering or in a related area with appropriate experience.
Minimum 5 years FPGA & HW development experience.
Strong leadership, interpersonal and observational skills.
Able to lead a team of diverse individuals.
Organized and very detail orientated.
Self-starter, quick learner and can work with minimum supervision in meeting schedules and project deadlines, balancing risks appropriately to optimize success across all business aspects – good, fast, and cheap.
Able to work independently or as part of a team.

Nice To Haves

Knowledge of television production.
An understanding of Digital video and audio standards.
Expertise in Video/Audio technologies.

Responsibilities

Develop and maintain high-level and detail design specifications (in conjunction with FPGA architects, system architects, Marketing and Product managers).
Work with FPGA developers to design, write, edit, and test FPGA coding as per the specifications or guidelines.
Oversee the development of FPGA design specifications, working with product managers, software design team and hardware design team.
Responsible for direction and coordination of the FPGA staff including the scheduling of tasks, verification of work, and monitoring progress.
Advise and make recommendations to management on matters relating to FPGA development, including toolset selection, methodologies and design guidelines, to provide them with an improved basis for decision making and planning.
Work with the team on scheduling and assigning verification and development tasks.
Assist manager in prioritizing bugs.
Responsibility for the load building and releasing for all the projects.
Schedule code inspections for the projects.
Support Hardware Manager and Project Managers as required.
Assist in training other staff members.
Perform other related duties as required.