Tapeout Mask Design Engineer

NVIDIA • Santa Clara, CA

3d

About The Position

NVIDIA is searching for an eager and motivated Senior Layout Mask Design Engineer to join the Advanced Technology Group. You will be responsible for fullchip DRC verification of testchips and products at NVIDIA. A successful candidate will have expertise in custom layout on state-of-the-art sub-micron CMOS technologies. As a tapeout engineer, this candidate should possess good interpersonal skills to communicate across NVIDIA design teams. What you will be doing: Perform physical layout of custom devices for ATG test-vehicles using industry layout tools, particularly Virtuoso. Debug fullchip DRC violations with verification tools such as Calibre and ICV. Collaborate with physical design engineers throughout Nvidia, directing designers on local layout fixes to resolve fullchip violations. What we need to see: A B.S. in EE/CS (or equivalent experience). 5+ years of industry experience in Mask Design; experience in fullchip is preferred. Deep understanding of layout concepts in submicron CMOS technologies. Expertise with Cadence custom circuit design tools, particularly Virtuoso. Experience running and debugging with verification tools such as Calibre and ICV. Good interpersonal skills to communicate across NVIDIA design teams. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 104,000 USD - 172,500 USD for Level 3, and 132,000 USD - 207,000 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until February 22, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Requirements

• A B.S. in EE/CS (or equivalent experience).
• 5+ years of industry experience in Mask Design; experience in fullchip is preferred.
• Deep understanding of layout concepts in submicron CMOS technologies.
• Expertise with Cadence custom circuit design tools, particularly Virtuoso.
• Experience running and debugging with verification tools such as Calibre and ICV.
• Good interpersonal skills to communicate across NVIDIA design teams.

Responsibilities

• Perform physical layout of custom devices for ATG test-vehicles using industry layout tools, particularly Virtuoso.
• Debug fullchip DRC violations with verification tools such as Calibre and ICV.
• Collaborate with physical design engineers throughout Nvidia, directing designers on local layout fixes to resolve fullchip violations.

Benefits

• You will also be eligible for equity and benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior