Substrate Packaging Defect Metro tool owner

Intel • Chandler, AZ

3d • Onsite

About The Position

We are seeking a motivated and skilled engineer to join our Advanced Packaging Technology and Manufacturing (APTM) Yield & Product Development team as a Substrate Packaging Defect Metro tool owner . In this role, you will play a critical part in enabling next‑generation advanced packaging technologies, including EMIB‑T, glass core, EMIB scaling, and panel‑level packaging, supporting both substrate and assembly test manufacturing (ATM) factories. Our goal is to be the supplier of choice for advanced, cost-effective substrate packaging by developing leading-edge systems, process capabilities, and inspection technologies to achieve top yields. Join us on our mission to make Intel a great workplace and industry leader. Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details. We are looking for individuals who are passionate about engineering excellence and sustainability. Apply today to help drive Intel's global impact through innovative packaging solutions.

Requirements

• Candidate must meet one of the following:
• Must possess a bachelor's degree in electrical engineering, Chemical Engineering, Optical Engineering, Materials Science, Physics or related field of study and 3 years of semi-conductor experience.
• Or a Master's degree in the same with 2 years of Semi-Conductor experience or a PhD Degree in the same with 1+ years of Semi-Conductor experience.
• Additionally, candidate must have 3+ years of experience in the following:
• Experience in micro-contamination management OR Bright / Dark field inspection technologies within a semiconductor manufacturing setting.
• Experience as a yield analyst or defect reduction owner or defect metrology tool ownership
• Strong technical ownership with the ability to work independently in a dynamic manufacturing environment
• Proactive problem‑solving and data‑driven decision‑making
• Effective cross‑functional collaboration with engineering, factory, and supplier partners
• Clear communication skills, including the ability to present complex technical topics to diverse audiences
• Adaptability and resilience in fast‑paced, high-change manufacturing environments

Nice To Haves

• Knowledge of statistics and experimental design and the skills to apply that knowledge tool qualification, and process development.
• Yield analysis, JMP/python scripting, equipment troubleshooting.
• Demonstrated understanding of semiconductor process flows and/or defect metrology assessment based on process requirements.
• Previous related work experience in a semiconductor foundry preferred.

Responsibilities

• Use defect inspection tools to detect and resolve process issues, collaborating with defect reduction, process integration, and module teams to improve yield.
• Apply real-time data analysis, reporting, and DOE summaries to guide improvements and decision-making.
• As a Micro-contamination and Defect metrology expert, apply advanced contamination detection and control strategies to maintain substrate and process quality.
• Lead efforts to monitor and reduce contamination, ensuring high yield and quality standards.
• Maintain flexibility and adaptability to support the evolving demands in micro-contamination management, responding to new challenges and requirements as they arise.
• Directed next-generation tool installation, reaching major milestones-purchase-spec : development, source inspection, design, prefac, Safety Level1/Safety Level2, Tool Qual, Supplier Qual, and Manufacturing readiness checklist -by collaborating with diverse stakeholders.
• Demonstrate the ability to manage work independently, proactively identifying and resolving issues with minimal supervision, and providing leadership in both defect metrology and micro-contamination initiatives.
• Work with factory teams and module partners to maintain WIP velocity targets in your area.
• Develop and roll out procedures and equipment setups for defect metrology tools to ensure they meet quality goals.
• Set up data flows for new tools by connecting them to automation and yield analysis systems, guaranteeing smooth performance and reliable data.
• Create and outline equipment roadmaps that support capabilities matching program requirements for new substrate technologies.
• Collaborate with equipment suppliers and GSEM partners to maintain current toolsets and enhance features, such as software and hardware upgrades, to satisfy Substrate packaging technology development program objectives.
• Present critical tool and system capabilities developed to meet program deliverables to APTM leadership, showcasing both defect metrology and micro-contamination expertise.

Benefits

• We offer a total compensation package that ranks among the best in the industry.
• It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level