Staff System Cache Architect and Design Engineer

Qualcomm • San Diego, CA

1d

About The Position

This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the use of EDA tools to execute the architecture and design of an individual block according to design protocol provided. Applies knowledge of memory systems including Cache Controllers, Memory Controller and LPDDR/DDR memory specifications, SRAM architectures, and latency/bandwidth tradeoffs to hardware design of the System Cache IP. Applies knowledge of Arm SoC Architecture, low power micro-architecture and hardware design concepts to deliver leading edge memory subsystem components for Qualcomm’s SoCs. Uses HDL languages (Verilog, SystemVerilog), know-how of front-end simulation tools (Synopsys Verdi), power analysis tools (Synopsys PTPX, synthesis tools like Synopsys Fusion Compiler), static timing analysis with Synopsys PrimeTime in day to day design tasks. Actively participates in microarchitecture development, RTL development, low power refinements, memory performance exploration, and meet area and timing goals for the hardware IP. Resolves architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision. Knowledgeable in RAS (Reliability, Availability and Serviceability) and ASIL (Automotive Safety Integrity Level) features and requirements for DRAM and memory subsystems. Strong knowledge of security and memory protection technologies like Arm Memory Tagging Extensions, Memory encryption algorithms such as AES, SHA-3. Strong knowledge on scripting languages, including C-shell/Perl/Python for design automation in addition to standard protocols such as Arm AXI, AXI-Streaming, AHB, APB interface specifications to integrate hardware components of the SoC. Provides ideas and furthers the innovation of ASICs, SoC, IP cores, and/or transistor level integrated circuits. Resolves architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision. Runs power checks on a single block to ensure it meets specifications provided by team lead. Interprets the results of performance checks and reports them to team lead. Provides input on process improvement by identifying existing resources or work products that can be reused or applied to assigned tasks. Owns the design and verification strategies of ASICs, SoC, and IP cores of a single block or IC Package. Mentors junior engineers and drives RTL and hardware development activities for the IP. Contributes to test plan development to identify edge/corner case bugs in the design and helps more junior team members do the same. Communicates directly with lead on any significant deviations from the Plan of Record for assigned block in a timely manner. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.

Requirements

• Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and two (2) years of experience in a related occupation.
• Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and seven (7) years of progressive experience in a related occupation.
• Knowledge of memory systems including Cache Controllers, Memory Controller and LPDDR/DDR memory specifications, SRAM architectures, and latency/bandwidth tradeoffs to hardware design of the System Cache IP.
• Knowledge of Arm SoC Architecture, low power micro-architecture and hardware design concepts to deliver leading edge memory subsystem components for Qualcomm’s SoCs.
• Uses HDL languages (Verilog, SystemVerilog), know-how of front-end simulation tools (Synopsys Verdi), power analysis tools (Synopsys PTPX, synthesis tools like Synopsys Fusion Compiler), static timing analysis with Synopsys PrimeTime in day to day design tasks.
• Knowledgeable in RAS (Reliability, Availability and Serviceability) and ASIL (Automotive Safety Integrity Level) features and requirements for DRAM and memory subsystems.
• Strong knowledge of security and memory protection technologies like Arm Memory Tagging Extensions, Memory encryption algorithms such as AES, SHA-3.
• Strong knowledge on scripting languages, including C-shell/Perl/Python for design automation in addition to standard protocols such as Arm AXI, AXI-Streaming, AHB, APB interface specifications to integrate hardware components of the SoC.

Responsibilities

• Leads, plans, synthesizes ambiguous or conflicting requirements.
• Performs the complex responsibility of the use of EDA tools to execute the architecture and design of an individual block according to design protocol provided.
• Applies knowledge of memory systems including Cache Controllers, Memory Controller and LPDDR/DDR memory specifications, SRAM architectures, and latency/bandwidth tradeoffs to hardware design of the System Cache IP.
• Applies knowledge of Arm SoC Architecture, low power micro-architecture and hardware design concepts to deliver leading edge memory subsystem components for Qualcomm’s SoCs.
• Uses HDL languages (Verilog, SystemVerilog), know-how of front-end simulation tools (Synopsys Verdi), power analysis tools (Synopsys PTPX, synthesis tools like Synopsys Fusion Compiler), static timing analysis with Synopsys PrimeTime in day to day design tasks.
• Actively participates in microarchitecture development, RTL development, low power refinements, memory performance exploration, and meet area and timing goals for the hardware IP.
• Resolves architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision.
• Knowledgeable in RAS (Reliability, Availability and Serviceability) and ASIL (Automotive Safety Integrity Level) features and requirements for DRAM and memory subsystems.
• Strong knowledge of security and memory protection technologies like Arm Memory Tagging Extensions, Memory encryption algorithms such as AES, SHA-3.
• Strong knowledge on scripting languages, including C-shell/Perl/Python for design automation in addition to standard protocols such as Arm AXI, AXI-Streaming, AHB, APB interface specifications to integrate hardware components of the SoC.
• Provides ideas and furthers the innovation of ASICs, SoC, IP cores, and/or transistor level integrated circuits.
• Runs power checks on a single block to ensure it meets specifications provided by team lead.
• Interprets the results of performance checks and reports them to team lead.
• Provides input on process improvement by identifying existing resources or work products that can be reused or applied to assigned tasks.
• Owns the design and verification strategies of ASICs, SoC, and IP cores of a single block or IC Package.
• Mentors junior engineers and drives RTL and hardware development activities for the IP.
• Contributes to test plan development to identify edge/corner case bugs in the design and helps more junior team members do the same.
• Communicates directly with lead on any significant deviations from the Plan of Record for assigned block in a timely manner.
• Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level