The Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects and Link interface units. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, and a solid foundation in verification methodology is required. The GPU Caches, Mem-Hierarchy Verification team is responsible for architectural and µ-architectural verification of sub-blocks within the memory hierarchy of the GPU like caches, interconnects and MMU Units. This role will grow your expertise in both software engineering as well as graphics hardware architecture and µ-architecture. As a member of this team, you will be responsible for authoring test plans for block or subsystem level functionality, architecting and developing highly complex verification software components, and working closely with design team members in debugging and closing the blocks you own. You will be able to work on test benches ranging from sub-blocks, blocks to subsystems containing multiple blocks.
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Job Type
Full-time
Career Level
Mid Level