Staff Engineer, Coherent Interconnect Design Verification

Samsung Electronics•Austin, TX

6d•$151,000 - $226,600

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Staff Design Verification Engineer, you will help lead the functional verification of System IP—including coherent interconnects, caches— through hands-on project execution. This high-impact individual contributor role requires strong expertise in design verification, testbench architecture, and methodologies across both block- and top-level environments. You will help define verification strategy, drive best practices, and ensure timely milestone execution in collaboration with global cross-functional teams to advance Samsung’s cutting-edge coherent interconnect IPs that power next-generation consumer mobile products. You ensure design excellence and thorough verification by contributing to key features, driving test planning, verifying design feature accuracy, and performing coverage analysis to identify improvement opportunities. You will develop reusable verification environments and testbenches, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints. You debug and root cause functional fails from regressions, and help with Silicon debug You perform coverage gap analysis, identifying coverage exclusions and improving stimulus You will be a key player in test plan and code reviews You will contribute to power-aware verification with UPF and gate-level simulations. You collaborative with design, SoC, physical design, and performance verification teams to debug failures, resolve spec issues, and enable successful bring-up across IP, SoC, and silicon. You exemplify an ownership culture and inspire an inclusive, high-performing culture by mentoring junior engineers, fostering trust, and data-driven decision-making through open communications. Our Team The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices. We play a critical role in shaping the technology roadmap, delivering scalable, performance- and power-optimized IP solutions that support advanced system modeling and real-world applications such as gaming and computational photography. With scalability and efficiency at the core of our designs, our IP integrates seamlessly into complex semiconductor products, enabling cutting-edge memory subsystem capabilities across diverse market segments. Joining our team means collaborating alongside talented engineers from diverse technical backgrounds across a global organization. You’ll have the opportunity to build next-generation technologies, broaden your expertise, and solve impactful challenges in a supportive environment built on collaboration, continuous learning, and growth.

Requirements

6+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 4+ years of experience with a Master’s degree, or 2+ years of experience with a PhD.
Must have experience with Interconnect
Proficiency in ARM protocols – CHI/AXI/ACElite, APB
Expert hands-on coding skills in System Verilog, UVM
Experience with Git version control, Unix/Perl scripting
Excellent communication and collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.

Responsibilities

help lead the functional verification of System IP—including coherent interconnects, caches— through hands-on project execution
define verification strategy, drive best practices, and ensure timely milestone execution in collaboration with global cross-functional teams
contributing to key features, driving test planning, verifying design feature accuracy, and performing coverage analysis to identify improvement opportunities
develop reusable verification environments and testbenches, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints
debug and root cause functional fails from regressions, and help with Silicon debug
perform coverage gap analysis, identifying coverage exclusions and improving stimulus
be a key player in test plan and code reviews
contribute to power-aware verification with UPF and gate-level simulations
collaborative with design, SoC, physical design, and performance verification teams to debug failures, resolve spec issues, and enable successful bring-up across IP, SoC, and silicon
exemplify an ownership culture and inspire an inclusive, high-performing culture by mentoring junior engineers, fostering trust, and data-driven decision-making through open communications