Staff DFT Timing Engineer

ARM • San Diego, CA

2d

About The Position

Arm's Solutions group DFT team implements DFT for SOC for client, datacenter, automotive, and IOT line of business using the latest DFT and process technologies. We Closely collaborate with Arm's partners and internal RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. We are currently hiring across three locations : San Jose , Austin , and San Diego .

Requirements

• This role is for a Staff DFT Timing Lead with 10+ years of experience in Design for Test.
• Stong understanding of DFT timing signoff constraints and modes!
• Experience in creating and validating DFT timing constraints in Geuns, Innovus, Fusion compiler, and PrimeTime.
• Familiarity with Synthesis and Static Timing Analysis.
• Familiarity with DFT architecture, components, and their interactions.
• Core DFT skills considered crucial for this position should include some of the following: experience in PrimeTime, Time-Vision, DFT timing constraints, Siemens DFT tool, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
• Experience coding Verilog RTL, TCL and/or Perl

Nice To Haves

• Familiarity with SoC style architectures including multi-clock domain and low power design practices.
• Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
• Background in high performance design, implementation and timing convergence is a plus
• Experience with 2.5D and 3D test
• Experience with Cadence, and/or Synopsys DFT and simulation tools
• Ability to work both collaboratively in a team and independently.
• Innovative and a passion for progress
• Hard-working and excellent time management skills with an ability to multi-task
• An upbeat approach to working on high-reaching projects on the cutting edge of technology!
• Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset

Responsibilities

• Lead DFT design and timing constraints to meet DFT logic PPA targets.
• Coordinate and drive the DFT requirements across SOC, IP and other product team to ease physical design closure effort.
• Develop and maintain methodology and flow related to DFT timing constraints generation, verification and closure
• Develop and validate DFT timing constraints in Geuns, Innovus, Fusion compiler, and PrimeTime.
• Collaborate with multi-functional team to ensure seamless closure of DFT logic timing, review DFT timing report and provide needed fixes.
• Insert DFT logic into SoC as well as sub-system level and validate all DFT features using industry standard simulation tools and collaborate in synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure activities

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed
• Number of Employees: 5,001-10,000 employees