Staff DFT Engineer

Celestial AI•Santa Clara, CA

4h•$225,000 - $245,000•Onsite

About The Position

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies. This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers. ABOUT THE ROLE We are looking for a Staff DFT Engineer with 8+ years of hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role focuses on end-to-end scan execution, from insertion and verification through DRC closure, coverage improvement, and final DFT signoff. The ideal candidate will own scan quality, coverage closure, and DFT signoff for complex SoC designs.

Requirements

Bachelor’s degree with 8+ years of relevant experience, OR Master’s degree with 6+ years of relevant experience
8+ years of hands-on experience in DFT scan implementation
Strong expertise with Siemens Tessent, including: Scan insertion and verification
ATPG pattern generation and coverage analysis
IJTAG (IEEE 1687) and SSN implementation
Strong understanding of: Scan Streaming Network (SSN)
IEEE 1149.x, IEEE 1500, and IEEE 1687 standards
Proven ability to resolve scan DFT DRCs and drive coverage closure
Strong TCL scripting skills for automation and flow customization
Experience developing and validating scan and test-mode timing constraints
Full DFT lifecycle experience, from RTL/netlist through silicon debug
Strong debugging, ownership, and problem-solving skills
Excellent verbal and written communication skills

Nice To Haves

Experience with scan compression and advanced scan architectures
Post-silicon experience, including: Pattern bring-up and debug
Silicon characterization and yield learning
Experience mentoring junior engineers or owning DFT scan signoff

Responsibilities

Lead hands-on scan DFT implementation, including: Scan insertion and stitching
Scan Streaming Network (SSN) implementation
IJTAG (IEEE 1687) insertion and connectivity
Perform scan DFT verification, debug, and DFT DRC closure
Debug and resolve scan-related DRCs, connectivity issues, and control signal problems
Run, analyze, and debug SpyGlass DFT/RTL checks, partnering with design teams to resolve violations
Generate, simulate, and debug ATPG scan patterns
Analyze ATPG results and drive scan coverage improvement and closure
Develop and validate DFT-related timing constraints (scan, shift, capture, and test modes)
Create and maintain TCL scripts for scan insertion, ATPG setup, and coverage analysis
Optimize scan implementations for pattern efficiency and test quality
Support hierarchical scan integration at both block and SoC levels
Collaborate closely with RTL and Physical Design teams to resolve scan-related issues
Support pre-silicon DFT signoff and post-silicon pattern bring-up and debug
Assist with ATE pattern conversion and scan debug activities

Benefits

We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.

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