Staff CPU RTL Design Engineer, Silicon

GoogleAustin, TX
9h$183,000 - $271,000

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 10 years of experience with CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
  • Experience with post-silicon CPU validation and hardware debugging, specifically for mobile device chips (phone-class SoCs).
  • Experience with RTL languages (System Verilog) and standard design processes (e.g., Lint, UPF).

Nice To Haves

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience leading front-end design for modern processor components or AI accelerators.
  • Experience with ARM Instruction Set Architecture and SOC design/integration.
  • Understanding of AMBA CHI (Coherent Hub Interface) and cache coherence protocols.

Responsibilities

  • Develop CPU subsystem front-end designs and microarchitecture, delivering high-quality RTL that meets frequency, power, and area (PPA) goals for next-generation processors.
  • Drive post-silicon CPU validation and debug for mobile/phone-class SoCs, focusing on hardware-software integration and debugging in real silicon.
  • Design and implement advanced designs in cache subsystems and/or vector arithmetic dataflow.
  • Propose performance-enhancing features and collaborate with Software, Architect, and Performance teams to conduct trade-off studies and communicate microarchitecture enhancements.
  • Stay current with modern design concepts and techniques, help in improving efficiency of the design processes.

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What This Job Offers

Job Type

Full-time

Career Level

Mid Level

Number of Employees

5,001-10,000 employees

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