Staff Central Hardware Systems - Architecture and Design Engineer

Qualcomm•San Diego, CA

1d•$154,000 - $231,000•Onsite

About The Position

CHS (Central Hardware Systems) Architecture and Design team at Qualcomm is looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work! By joining our team, you’ll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on designing XR packages and systems based on Qualcomm's Snapdragon SoC. As an experienced CHS-AAD Engineer (individual contributor), you will collaborate with various cross-functional teams, including Technology team, SIPI, PDN, PCB design team, product management, and Chipset team. You will be responsible for creating high-performance package/SIPs designs and ensuring their successful transition to production for our XR products Position requires to be in San Diego full time, 5 days a week

Requirements

Master's degree in Electrical or Computer Engineering or a related field.
7+ years of experience in package/SIP/PCB hardware design.
Expertise designing high-speed, dense, multi-layer Packages, PCBs and systems.
Proficiency in logic design, schematic capture, board layout tools, and testing.
Strong knowledge of SIPI, PDN, thermal management, and compliance testing.
Expertise in high-speed analog and digital design.
Hands-on experience with PCIe, DDR, Ethernet, SerDes, and communication protocols (I2C/I3C/SPI/MDIO).
Proven ability to work independently and collaboratively within a cross-functional team environment.
Strong technical documentation skills and excellent written and verbal communication.
Bachelor's degree in Electrical Engineering, Computer Science, or related field and 9+ years of Systems Engineering or related work experience.
Master's degree in Electrical Engineering, Computer Science, or related field and 7+ years of Systems Engineering or related work experience.
PhD in Electrical Engineering, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.
Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ years of System/Package Design/Technology Engineering or related work experience.
Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 3+ years of System/Package Design/Technology Engineering or related work experience.
PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 2+ year of System/Package Design/Technology Engineering or related work experience.

Nice To Haves

PhD degree in Electrical or Computer Engineering or a related field.
5+ years of experience in package/PCB design.
In-depth knowledge of PMIC, RF front end, Memories
Working knowledge with scripting languages (Python, PERL, TCL).

Responsibilities

IC top level floorplanning and understanding of hard macro block placement, padring, RDL and bump pattern/assignment.
System level co-design methodology of IC, Package and PCB/Board.
Concept analysis for new product package selection based on requirements for mechanical, thermal and electrical performance with the goal to achieve lowest system level cost.
Package design flow methodology implementing high speed interface SI constraints for jitter, IR drop, cross-talk, and SSN specs.
Experience with ORCAD schematic and Allegro design tools.
Package design flow methodology implementing power distribution network (PDN) constraints for high speed processor cores (1GHz+) including design optimization techniques at the die/pkg/PCB levels.
Understanding on PMIC and its eBOM.
Designing PDN from PMIC to SOC to meet the given targets.
Working with marketing/IC/product teams on competitive analysis and road mapping package technology for future products
Designing High speed interfaces.
Verification for packages and sips using Valor and ravel checks.
Design review with suppliers and Osats.
Evaluations on optimizing cost and area for a given package/SIP structure.