Sr Technical Marketing Architect - Datacenter & AI Systems
About The Position
Lattice Semiconductor is seeking a Senior Technical Marketing Architect to define and drive next-generation datacenter and AI system architectures. This role blends deep system design expertise with strategic marketing and ecosystem engagement-identifying where Lattice FPGAs add value in control, orchestration, and security across compute, storage, and networking. The ideal candidate understands hyperscaler hardware, manageability, and rack-scale design, and can spot new sockets where deterministic, low-latency programmable logic outperforms fixed-function devices.
Requirements
- BS/MS in Electrical, Computer, or Systems Engineering.
- 12+ years in datacenter hardware architecture, technical marketing, or system design.
- Expertise in platform manageability and control (BMC, RMC, attestation, telemetry).
- Knowledge of datacenter storage, networking, and power systems (PCIe/CXL, NVMe, Ethernet, cooling).
- Familiarity with LTPI, SPDM, PLDM, and other DMTF and OCP standards.
- Proven ability to translate architectures into strategies and drive ecosystem adoption.
- Experience working with hyperscalers, OEMs, or SoC vendors on validation and deployment.
- Excellent communication and executive presentation skills.
Nice To Haves
- Experience in rack-scale orchestration, AI cluster, or fabric management.
- Knowledge of FPGA/CPLD integration in control, telemetry, or security roles.
- Understanding of AI server architectures, accelerators, and thermal/power management.
- Published contributions to industry standards or specifications.
Responsibilities
- Architect datacenter control solutions across compute, storage, and network domains, including BMC, RMC, and rack orchestration.
- Identify and define FPGA attach points for telemetry, power/cooling control, fabric management, and secure boot.
- Shape technical marketing strategy for AI and datacenter platforms-developing MRDs, reference architectures, and partner programs.
- Collaborate with SoC, CPU, DPU, and accelerator vendors to co-design FPGA-enhanced system solutions.
- Engage with CSPs, OEMs, and ODMs to translate requirements into FPGA-based proofs of concept.
- Drive technical narratives that showcase Lattice leadership in control, security, and system orchestration.
- Align with product and engineering teams to ensure design integrity, validation, and roadmap coherence.
- Represent Lattice in OCP, DMTF, and related forums to guide standards and influence ecosystem direction.
Benefits
- The base pay for this role is between $180,000 to $230,000 per year in the Bay Area. Compensation will align with the local markets in other areas.
- In addition to base salary, we offer an incentive plan bonus and new hire equity for a competitive total compensation package.
- Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Industry
Computer and Electronic Product Manufacturing
Number of Employees
501-1,000 employees
