Sr Staff CPU Core/Unit Verification Engineer, Functional Safety
About The Position
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a passionate and detail-oriented Design Verification Engineer to join our Functional Safety (FuSa) IP team. You will work on verifying safety-critical IPs designed to meet ISO 26262/ASIL-B/ASIL-D and similar safety standards, ensuring correctness, robustness, and resilience. The ideal candidate will bring strong verification fundamentals and an interest (or experience) in safety verification.We welcome candidates at various experience levels for this role. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Requirements
- Experienced DV engineer with SystemVerilog, C++ and UVM expertise.
- Strong interest in safety-critical design and understanding of ISO 26262 ISO (ASIL levels B–D). or other safety standards.
- Able to work independently and deliver in a highly accountable environment.
- Team player who communicates clearly and thrives in cross-functional teams.
- Ability to build C++/UVM environments and author safety-focused test plans.
- Experience with fault injection, resilience testing, or safety diagnostics.
- Hands-on experience with Synopsys VC Z01X, Siemens Tessent or Cadence Safety Verification for fault simulation and analysis.
Responsibilities
- Work closely with safety architects and designers to validate safety mechanisms and
- Analyze fault simulation results to measure and report diagnostic coverage (SPFM, LFM, PMHF).
- Ensure traceability of safety requirements from PRD → RTL → testbench → Stimulus → results.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
Number of Employees
501-1,000 employees
