Sr Physical Design Engineer (Remote)
About The Position
Sr Physical Design Engineer (Remote) Full-time: Salary + Benefits + Bonuses / Contractor Work Status: US citizen or Lawful Permanent Resident. Remote (Anywhere in US) Responsibilities Lead full-chip and block-level physical design for advanced semiconductor products across multiple technology nodes. Define and drive chip floorplanning, power and clock architectures, placement and routing, and chip assembly. Own timing closure, signal integrity, power, noise, yield, and physical verification (DRC/LVS) through sign-off. Architect and implement solutions for complex multi-voltage, multi-clock domain and IO designs, including custom routing of critical paths. Establish, improve, and scale physical design methodologies, automation, and RTL-to-GDS flows. Provide technical leadership across cross-functional and global teams, driving closure on performance, quality, and schedule. Review and approve physical design deliverables for manufacturing readiness. Mentor engineers influence best practices and contribute to technical roadmap decisions. Qualifications Min 8+ years of experience in physical design and sign-off for advanced semiconductor technologies. Proven leadership in full-chip and hierarchical implementations. Deep expertise in P&R, static timing analysis, DRC/LVS, power, and noise analysis. Strong experience with industry EDA tools (Cadence, Siemens/Mentor, or equivalent). Advanced scripting and automation skills (Tcl, Perl, Python, Skill). Experience with advanced process nodes (e.g., 14nm and below) strongly preferred. The anticipated annual base salary for this position is between $130,000 to $150,000, which also includes a comprehensive benefits package. Full-Time Benefits: 15 days of PTO per calendar year 10 paid Holidays per calendar year Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents Dental & Vision: Company covers 50% of premiums for Employee and Dependents Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance Employee Assistant Program (EAP) 401k - Traditional & Roth Life/AD&D and Long-Term Disability Tuition reimbursement Equal Opportunity Policy Statement Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances. Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Requirements
- Min 8+ years of experience in physical design and sign-off for advanced semiconductor technologies.
- Proven leadership in full-chip and hierarchical implementations.
- Deep expertise in P&R, static timing analysis, DRC/LVS, power, and noise analysis.
- Strong experience with industry EDA tools (Cadence, Siemens/Mentor, or equivalent).
- Advanced scripting and automation skills (Tcl, Perl, Python, Skill).
Nice To Haves
- Experience with advanced process nodes (e.g., 14nm and below) strongly preferred.
Responsibilities
- Lead full-chip and block-level physical design for advanced semiconductor products across multiple technology nodes.
- Define and drive chip floorplanning, power and clock architectures, placement and routing, and chip assembly.
- Own timing closure, signal integrity, power, noise, yield, and physical verification (DRC/LVS) through sign-off.
- Architect and implement solutions for complex multi-voltage, multi-clock domain and IO designs, including custom routing of critical paths.
- Establish, improve, and scale physical design methodologies, automation, and RTL-to-GDS flows.
- Provide technical leadership across cross-functional and global teams, driving closure on performance, quality, and schedule.
- Review and approve physical design deliverables for manufacturing readiness.
- Mentor engineers influence best practices and contribute to technical roadmap decisions.
Benefits
- 15 days of PTO per calendar year
- 10 paid Holidays per calendar year
- Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
- Dental & Vision: Company covers 50% of premiums for Employee and Dependents
- Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
- Employee Assistant Program (EAP)
- 401k - Traditional & Roth
- Life/AD&D and Long-Term Disability
- Tuition reimbursement
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
