Sr. Hardware-in-the-Loop Engineer

Xona Space Systems•Burlingame, CA

About The Position

Xona is the navigational intelligence company bringing real-time, centimeter-level certainty to any device, anywhere on Earth. With Pulsar – the world’s most advanced PNT satellite infrastructure in Low Earth Orbit – Xona will offer a future-proof, backwards-compatible global positioning system optimized for absolute precision, superior power, and robust protection. As a Senior Hardware-in-the-Loop (HIL) Engineer, you’ll be a primary contributor to the design, build-out, and operation of integrated spacecraft testbeds. You will connect flight hardware (or engineering models) to high-fidelity simulations and automated test infrastructure to validate flight software, avionics interfaces, fault management behaviors, and operational workflows end-to-end—well before launch. You will also own the HIL software stack that powers the testbed, ensuring it is maintainable, extensible, and trusted as a program-critical validation environment.

Requirements

Experience: 7+ years in system integration, HIL/SIL environments, or embedded hardware/software validation, with demonstrated ownership of testbed capabilities.
HIL Software: Proven ability to design and maintain a production-quality HIL software stack (test orchestration, interface layers, telemetry tooling, fault injection, reporting).
Integration & Testing: Track record executing full-system validation campaigns, including fault injection and performance characterization.
Protocols & Interfaces: Strong practical expertise with embedded buses and lab instrumentation strategies (RS-422/485, Ethernet, I2C/SPI, etc.).
Real-Time Systems: Solid understanding of timing, scheduling, latency, and resource constraints in integrated systems.
Communication: Strong written documentation and cross-team coordination skills.
For U.S. Roles: To comply with U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the United States (i.e. Green Card holder), or other protected individual as defined by 8 U.S.C. 1324b(a)(3).
For U.K. Roles: To comply with U.K. regulations, this role requires Baseline Personnel Security Standard (BPSS) checks, and successful candidates must be eligible to obtain UK Security Clearance (SC).
For Canada Roles: Successful candidates must obtain and hold a security clearance at the reliability status level, and pass security assessment for the Canadian Controlled Goods Program (CGP) and ITAR.

Nice To Haves

Experience supporting on-orbit operations, telemetry analysis, mission rehearsals, or anomaly investigations using integrated testbeds.
Background in aerospace or other safety-/mission-critical environments with strong validation culture.
Familiarity with flight software frameworks (cFS, F’, TASTE, etc.) and real-time concepts.

Responsibilities

Own the HIL software stack end-to-end, including architecture, code quality, documentation, and long-term maintainability.
Develop the core HIL software components that orchestrate hardware, simulation, command/telemetry, and test execution—carrying features from concept through validated, reusable capability.
Build and maintain hardware abstraction layers and interface adapters for avionics buses and lab instrumentation (e.g., RS-422/485, Ethernet, I2C/SPI, GPIO, DAQ, power systems).
Implement fault-injection services in software (bus faults, packet corruption, timing faults, power cycling hooks, sensor/actuator emulation errors) to systematically validate FDIR and operational mitigations.
Create and maintain telemetry/command tooling for the HIL environment (collection, decoding, time correlation, replay, and analysis), enabling rapid triage and regression insight.
Architect and assemble HIL environments combining flight computers, avionics I/O, sensors/actuators (or emulators), and real-time simulation.
Own the lab bring-up workflow: wiring, timing/latency characterization, configuration baselines, and repeatable testbed provisioning.
Plan and execute comprehensive hardware/software integration campaigns, including nominal mission threads, off-nominal scenarios, and “day-in-the-life” sequences.
Define measurable acceptance criteria for integrated behaviors (timing budgets, throughput, fault response, recovery time objectives)
Define and validate system interfaces across embedded buses and protocols; verify ICD compliance through test evidence.
Measure and troubleshoot real-time system behavior (scheduler jitter, end-to-end latency, throughput, CPU/memory pressure under load).
Support performance benchmarking and stress testing to expose “edge-of-envelope” behaviors before flight.
Build automation for test orchestration, data capture, and reporting—prioritizing repeatability and high signal-to-noise.
Integrate HIL regression into CI/CD where feasible (gated runs, nightly suites, artifact retention, log/telemetry indexing).
Improve testbed reliability via configuration management, scripted provisioning, and robust runbooks.
Partner with flight software, hardware engineering, GNC, and operations to turn requirements into verifiable test objectives and executable procedures.
Drive alignment on fault handling, safe-mode behaviors, and on-orbit mitigation workflows—then validate them in HIL.
Lead investigations into intermittent integration failures and close the loop with corrective actions across software, hardware, and process.
Produce technical artifacts: HIL architecture docs, lab procedures, interface validation checklists, test plans, and runbooks.
Coach engineers through design reviews and code walks; promote disciplined debugging, coding standards, and automation-first testing.
Want technical ownership of both the physical HIL environment and the software platform that makes it scalable and credible.
Enjoy hands-on integration and can translate ambiguous system behavior into crisp hypotheses, instrumentation, and repeatable tests.
Are meticulous about timing, interfaces, and fault behavior—and can build tooling that makes those characteristics visible.
Communicate clearly across teams and can drive interface clarity and operational readiness through test evidence.