Sr. ASIC Design Engineer, Amazon Leo

Amazon • Austin, TX

8d

About The Position

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit
satellites that will provide low-latency, high-speed broadband connectivity to
unserved and underserved communities around the world.

Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S.
citizen or national, U.S. permanent resident (i.e., current Green Card holder),
or lawfully admitted into the U.S. as a refugee or granted asylum.

Be part of Amazon LEO’s sub-team responsible for defining and implementing the
digital chip SOCs for communications via Low Earth Orbit satellites and Amazon
gateways. This is a unique opportunity to define a groundbreaking wireless
solution with few legacy constraints. The team works with customer requirements
and wireless system teams to define modems, high-speed interfaces, embedded
processors, and DSP solutions in latest CMOS generation technologies.

Requirements

• 8+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
• 8+ years of digital design in communication systems experience
• 8+ years of wireless communications systems and implementation experience
• Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering
• Knowledge of implementing chips with multiple power islands and power gating
• Knowledge of serial protocols including SPI, I2C, I3C, and UART
• Knowledge of Python and Embedded C programming
• Experience low power design techniques
• Experience leading technical initiatives and key deliverables
• Experience with version control systems and CI/CD pipeline implementation

Nice To Haves

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
• Experience with modern ASIC/FPGA design and verification tools
• Experience with SOC bring-up and post-silicon validation

Responsibilities

• RTL Design and development of custom blocks.
• Integration of large subsystems
• Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure design closure.
• Facilitate seamless integration across Firmware, RTL, Platform Software, and Platform Drivers.
• Develop Debug tools: RTL Emulation, silicon bring-up, and functional validation.
• Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets.
• Define, configure and integration SoC Subsystems
• Contribute to the SoC floor planning effort
• Define and develop any necessary support logic
• Configure, instantiate and integrate 3rd party IP blocks
• Understand low power design & the impact of DFT on the blocks
• Perform initial synthesis & timing analysis
• Assist verification team in unit verification including test plan development
• Assist with debug and bring-up

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level