Sr. ASIC Design Engineer (Silicon Engineering)

Space Exploration Technologies•Irvine, CA

33d•$160,000 - $220,000

About The Position

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

Requirements

Bachelor's degree in electrical engineering, computer engineering, or computer science
5+ years of experience in RTL implementation

Nice To Haves

Ability to solve complex problems including clock domain crossings and power optimization
ASIC/SoC system integration experience
Experience with multicore CPU subsystem design
Experience with standard bus protocols (e.g. AXI, AHB, etc.)
Experience with embedded processors
Experience with high speed and low power design techniques
Scripting skills (Python, TCL etc.)
Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
Ability to work in a dynamic environment with changing needs and requirements
Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
Enjoys being challenged and learning new skills

Responsibilities

Evaluate architectural trade-offs based on features, performance requirements and system limitations
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
Work closely with verification team to ensure all aspects of the design are covered and verified
Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
Participate in silicon bring-up and validation

Benefits

long-term incentives, in the form of company stock, stock options, or long-term cash awards
potential discretionary bonuses
ability to purchase additional stock at a discount through an Employee Stock Purchase Plan
comprehensive medical, vision, and dental coverage
access to a 401(k) retirement plan
short & long-term disability insurance
life insurance
paid parental leave
various other discounts and perks
3 weeks of paid vacation
10 or more paid holidays per year
5 days of sick leave per year