Principal ASIC Design Engineer (Silicon Engineering)

SpaceX•Irvine, CA

About The Position

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science
10+ years of experience in RTL implementation and/or FPGA/ASIC development

Nice To Haves

Experience solving problems including clock domain crossings and power optimization
Experience developing complex ASICs
Experience with multicore CPU subsystem design
Experience with standard bus protocols (e.g. AXI, AHB, etc.)
Experience with embedded processors
Experience with high speed and low power design techniques
Scripting skills (Python, TCL etc.)
Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
Ability to work in a dynamic environment with changing needs and requirements
Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
Enjoys being challenged and learning new skills

Responsibilities

Design digital ASICs and/or FPGAs for Starlink projects
Evaluate architectural trade-offs based on features, performance requirements and system limitations
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
Work closely with verification team to ensure all aspects of the design are covered and verified
Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
Participate in silicon bring-up and validation

Benefits

You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks.
You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year.
Exempt employees are eligible for 5 days of sick leave per year.

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