Principal Engineer ASIC/Layout Design

Infineon•Andover, MA

About The Position

Principal Layout engineer responsible for Layout of top and block level schematics Responsible as Lead Layout support product development and TO activities Implement Physical layout at block and top levels utilizing best practices for matching, shielding, dummies, fills, and isolation. Work with design engineers on sizing and matching trade off on the block level. Provide floor planning strategy for different power management IC’s. Create tape out documentation including LVS, ERC and DRC checks on block and top level. Work with technology and pdk engineers to understand and if possible eliminates all non relevant DRC errors As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels. We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Driving decarbonization and digitalization. Together.

Requirements

Experience with Tape out procedures
Associate or Bachelors in EE or other equivalent studies with 10+ years of relevant experience, preferred in Analog layout
Experience with Cadence Virtuoso, Assura, and Calibre with an understanding of PDK’s, PCELL’s, layers, etc.
The successful candidate will need to be a very organized and detail oriented individual.
The candidate will be required to communicate well and work well with team members.
The candidate must also be highly motivated, innovative, and capable of driving tasks to a successful conclusion.
Thorough knowledge of industry standard EDA tools from Cadence.
Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence tools.
Experience with layout of high power power management IC’s.
Experience with floor planning, die size estimates, block level routing and top level chip assembly.
Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience working with remote design teams.
Reading and interpreting Design Rule Manuals.

Responsibilities

Principal Layout engineer responsible for Layout of top and block level schematics
Responsible as Lead Layout support product development and TO activities
Implement Physical layout at block and top levels utilizing best practices for matching, shielding, dummies, fills, and isolation.
Work with design engineers on sizing and matching trade off on the block level.
Provide floor planning strategy for different power management IC’s.
Create tape out documentation including LVS, ERC and DRC checks on block and top level.
Work with technology and pdk engineers to understand and if possible eliminates all non relevant DRC errors
Guide and train junior engineers.