SOC RTL Integration Engineer

Advanced Micro Devices, Inc•San Jose, CA

8d•Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Building full-chip RTL connectivity models. Integrating RTL components from multiple design teams. Verifying that full chip models match architectural intent. Developing custom tools and methodologies to improve development efficiency and quality We are currently seeking professionals with experience in SOC RTL or Front-End integration, possessing strong expertise in timing constraints development and validation, including proficiency with Fishtail, PrimeTime and SDC development. If you have a proven track record in developing and validating robust timing solutions for complex chip designs, we invite you to join our team focused on advancing innovative semiconductor technologies. The right candidate will focus on full-chip RTL development and integration for next generation FPGA and programmable SoC products. The candidate must be able to work with team members in globally diverse regions. A positive attitude and strong personal desire to "make a difference'. A self-starter who demonstrates an ability to work on own as well within a team.

Requirements

Experience in SOC RTL or Front-End integration
Expertise in timing constraints development and validation
Proficiency with Fishtail, PrimeTime and SDC development

Nice To Haves

Strong experience using FPGAs and understanding FPGA architectures in a semi conductor environment
Proven experience with timing tools such as primetime and fishtail
Proven experience with stages in the ASIC design flow including verification methodologies and tools (UVM/OVM, Formal Checks, Lint tools, etc.)
Knowledge in RTL and behavioral coding, preferably with Verilog and SystemVerilog
Good waveform debug skills using front end industry standard design tools like VCS, NC Sim, or Verdi
Knowledge of Unix/Linux environment and scripting languages such as Perl or Python
Some Experience using Revision Control tools – CVS, Subversion, or Perforce
Presentation Skills

Responsibilities

Develop Full Chip SOC RTL
Develop timing constraints and validate them
Write Full Chip Design Specification document
Work with IP development team to integrate IPs
Work across architecture, SW and verification teams to assure Full Chip SOC RTL quality
Run lint and cdc tools and generate timing constraints