Senior Design Engineer (SoC RTL)

NXP Semiconductors•San Diego, CA

About The Position

Senior Design Engineer (SoC RTL) NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 29,000 employees in more than 30 countries and posted revenue of $8.61 billion in 2020 Business Line Description We are part of ACE Engineering, a central design organization within NXP, Implementing designs for multiple business lines in Automotive, Internet of Things (IoT), Digital Networking Job Summary: Building Subsystems and/or SoC RTL integration for Internal or Vendor driven IPs like ARM Cores, DDR, PCIe, Ethernet, DSP/AIML cores, GPU, VPU, MIPI-CSI, USB, Display Controller Write Micro-Architecture and detailed design specification in close collaboration with architecture, circuit designers, DFT/Physical Design/Verification engineers. Provide high-quality RTL description, including assertions, for the design. Perform all aspects of the SoC design flow from high level design to Synthesis. Key Challenges: The team works on Best in class Leading technologies designing chips for future Autonomous EVs or IoT Devices. Being life-critical application, all engineers are trained on Functional Safety and Design Quality standards to ensure correct by construction architecture and designs. Perform concept studies and provide direction in terms of performance, gate count and power for various digital designs. Existing team is a mix of Design Architects, Domain experts and Tools/Flows/Methodology/Process champions - Right set of people who can own full chip from Definition to Production. Team is groomed to demonstrate right set of values like Customer First, Ownership, Collaboration, Speed and Quality. Great opportunities to innovate with supportive and encouraging environment, converting into Patents, Defensive Publications and Trade Secrets with generous rewards. Cross functional aspects: The team members own and gain expertise in their specific areas of assignment, while collaborating with Global stakeholders. The role also involves contributing to improvements in Tools, Flows and Methodologies across global design community, interacting with global sites. There are opportunities to work in wide range of domains and learning through cross-functional handoffs and interactions

Requirements

MS or PhD in Electrical/Electronic/ Computer Engineering
Requires 8+ years of experience in high performance digital logic designs and SoC Integration using ARM Cores, Bus Protocols and Interconnects
Must have expertise on RTL Sign off checks (LINT, CDC, RDC, LEC, UPF)
Experience with Synopsys VCS or Cadence RTL simulator, Design Complier (DC) or RTL Compiler (RC or Genus), Verdi Debugging tool
Self-motivated with Excellent written and verbal communication skills
Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components
Should be a team player and willing to work with cross functional teams in issues resolution
Experience collaborating with international teams
Experience mentoring junior team members and overseeing their work

Nice To Haves

Clock/Reset/Power Management Architecture would be a plus
Logic Synthesis and Timing Closure, Netlist ECO would be a plus
ISO26262 based functional safety relevant microcontroller architectures is a plus

Responsibilities

Building Subsystems and/or SoC RTL integration for Internal or Vendor driven IPs like ARM Cores, DDR, PCIe, Ethernet, DSP/AIML cores, GPU, VPU, MIPI-CSI, USB, Display Controller
Write Micro-Architecture and detailed design specification in close collaboration with architecture, circuit designers, DFT/Physical Design/Verification engineers.
Provide high-quality RTL description, including assertions, for the design.
Perform all aspects of the SoC design flow from high level design to Synthesis.
Perform concept studies and provide direction in terms of performance, gate count and power for various digital designs.
Contributing to improvements in Tools, Flows and Methodologies across global design community, interacting with global sites.