SOC IP Methodology Engineer - Custom SOC

NVIDIA•Santa Clara, CA

About The Position

Nvidia is hiring a Senior SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP solutions. We are looking for individuals with passion and desire to deliver innovative products. Together, we will build the next generation of life changing SoC’s. If you are a motivated individual that understands how SoC systems are architected and built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be. What you will be doing: Responsible for developing and optimizing semi-custom RTL to GDS methodologies, work with internal and external collaborators and IP Vendors on SOC/IP requirements and drive technology alignments across them. You will be a hands-on domain expert, able to traverse from Synthesis to final design closure (timing and layout) involving latest EDA technologies and capabilities. Work with customers on SOC/IP development processes, IP quality and handoff requirements for QA, smooth integration, and high-quality analysis flows. You will drive, review, and cultivate development processes to assure top quality work to and from IP customers and SOC engineers. You will help in driving technical design reviews, assuring that defined processes are followed, identifying, and mitigating risks, and continuing to improve development processes with innovative tools and procedures. Be responsible for results/handoffs to and from Customers, methodology solutions and schedule plans. You will be required to drive early PPA on customer IP and drive what-if experiments to help drive KPI targets, analyze and solve critical issues Will work with internal and external collaborators to carry out floorplan experiments to drive area estimates and evaluate solution tradeoffs. Work with Nvidia PD design methodology team to come up with best methodologies to integrate external customer IP. You will also work with external ASIC companies if we decide to outsource some part of Nvidia design. What we need to see: Masters with 8+ (or BS or equivalent experience with 10+) years of experience within these skill areas. Extensive leadership experience as Methodology and Technical expert in physical design working with internal and external partners Experience working in a SOC development and customer focused environment with excellent interpersonal skills. Experience in handling complex IP ecosystem involving both internal and external partners. Exposure to IP-XACT or similar infrastructure is a plus. Proven hands-on experience with RTL-to-GDSII tool flows. physical design and analysis tools from EDA vendors such as Cadence, Synopsys, Mentor (CDC, LP Checks, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT-SI, Tempus, Redhawk) etc. Understanding of full flow (including DFT, BIST) to integrate customer and third-party IP and drive program alignment. Proven abilities to optimize methodology and flows for high productivity, design optimization and incorporate innovation. Strong background and knowledge in Synthesis, CTS, Power Optimization, Placement and Route methods and timing convergence for high performance designs like CPU, GPU and machine learning IPs. Strong scripting skills involving Python, Perl and Tcl, excellent soft skills. RTL2GDS experience with high performance ARM cores, Serdes, DDR, GPU, machine learning experience would be a plus. With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us, and, due to outstanding growth, our special engineering teams are growing fast. If you're a creative and autonomous professional with a genuine passion for technology, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until January 24, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Requirements

Masters with 8+ (or BS or equivalent experience with 10+) years of experience within these skill areas
Extensive leadership experience as Methodology and Technical expert in physical design working with internal and external partners
Experience working in a SOC development and customer focused environment with excellent interpersonal skills
Experience in handling complex IP ecosystem involving both internal and external partners
Proven hands-on experience with RTL-to-GDSII tool flows
physical design and analysis tools from EDA vendors such as Cadence, Synopsys, Mentor (CDC, LP Checks, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT-SI, Tempus, Redhawk) etc
Understanding of full flow (including DFT, BIST) to integrate customer and third-party IP and drive program alignment
Proven abilities to optimize methodology and flows for high productivity, design optimization and incorporate innovation
Strong background and knowledge in Synthesis, CTS, Power Optimization, Placement and Route methods and timing convergence for high performance designs like CPU, GPU and machine learning IPs
Strong scripting skills involving Python, Perl and Tcl, excellent soft skills

Nice To Haves

Exposure to IP-XACT or similar infrastructure is a plus.
RTL2GDS experience with high performance ARM cores, Serdes, DDR, GPU, machine learning experience would be a plus

Responsibilities

Responsible for developing and optimizing semi-custom RTL to GDS methodologies
Work with internal and external collaborators and IP Vendors on SOC/IP requirements and drive technology alignments across them
Traverse from Synthesis to final design closure (timing and layout) involving latest EDA technologies and capabilities
Work with customers on SOC/IP development processes, IP quality and handoff requirements for QA, smooth integration, and high-quality analysis flows
Drive, review, and cultivate development processes to assure top quality work to and from IP customers and SOC engineers
Drive technical design reviews, assuring that defined processes are followed, identifying, and mitigating risks, and continuing to improve development processes with innovative tools and procedures
Be responsible for results/handoffs to and from Customers, methodology solutions and schedule plans
Drive early PPA on customer IP and drive what-if experiments to help drive KPI targets, analyze and solve critical issues
Work with internal and external collaborators to carry out floorplan experiments to drive area estimates and evaluate solution tradeoffs
Work with Nvidia PD design methodology team to come up with best methodologies to integrate external customer IP
Work with external ASIC companies if we decide to outsource some part of Nvidia design