Senior Emulation Methodology Engineer

Advanced Micro Devices, Inc•Austin, TX

10h•Hybrid

About The Position

Join AMD’s Emulation and Prototyping Methodology team and help define how next‑generation products are validated and delivered. In this role, you will shape advanced hardware/software methodologies and tools that accelerate product readiness across RTL validation, debugging, and pre‑/post‑silicon workflows. You will partner closely with engineering leaders across the company to build scalable, efficient, and forward‑looking approaches that improve productivity and enable rapid innovation. THE PERSON You are a technical leader who enjoys solving complex problems, driving clarity, and fostering collaboration. You learn new technologies quickly, think strategically about methodology improvements, and build tools and processes that help teams work smarter. You communicate effectively and create strong partnerships that enable teams to achieve ambitious goals together.

Requirements

Strong analytical and debugging skills, with the ability to drive solutions in complex technical environments.
Experience with one or more emulation/prototyping platforms (e.g., Veloce, Palladium, Protium, Zebu, HAPS).
Understanding of CPU/GPU architecture and protocols such as PCIe, DRAM, Ethernet, AMBA, or CXL.
Background in RTL design, verification, or embedded firmware/BIOS.
Proficiency in System Verilog, C++, Perl, or Python, or the ability to learn them quickly.
Familiarity with transactors and C‑DPI methodologies for emulation.
Experience with waveform analysis tools (e.g., Verdi or Visualizer).

Nice To Haves

Awareness of hybrid emulation technologies.

Responsibilities

Lead cross‑functional collaboration to develop and deploy methodologies that optimize emulation and prototyping environments and improve time‑to‑market.
Apply platform knowledge to address challenges across infrastructure, design implementation, firmware, and software workloads.
Research, evaluate, and integrate new technologies that enhance pre‑silicon validation efficiency and scalability.
Partners with vendors to define and deploy platforms that meet performance goals (compile time, runtime, capacity, test execution).
Integrate and enable verification interfaces including PCIe, memory device models, UART, JTAG, I2C, USB, and Ethernet.
Leverage ML/AI techniques to scale and automate emulation workflows.
Work closely with EDA partners to incorporate emerging capabilities into AMD’s development environment.