Lead Emulation Engineer

Positron Corporation

8h

About The Position

As a Lead Emulation Engineer, you will provide technical leadership for the pre-silicon validation of Positron.ai’s next-generation AI inference ASIC. You will own the end-to-end emulation strategy on the Cadence Palladium platform—architecting complex model builds, managing multi-rack partitioning, and driving the 'left-shift' of our software development. You will collaborate across RTL, DV, and Software teams to build high-performance virtual environments that prove out architectural functionality and accelerate firmware/OS bring-up months before tape-out. This role is critical to our silicon success: you will set the emulation methodology, resolve hardware-software bottlenecks at scale, and ensure our design is silicon-ready.

Requirements

• Deep Palladium Expertise: Extensive hands-on experience with Cadence Palladium (Z1/Z2/Z3), including advanced clocking, ICE (In-Circuit Emulation), and Virtual Interface (VIF) flows
• Complex SoC Background: A track record of emulating multi-billion gate designs where partitioning, runtime predictability, and compile efficiency were critical success factors
• Automation Mastery: Expert-level Python, Tcl, and Bash skills to build and maintain the infrastructure for automated model releases and nightly regressions
• Hardware-Software Debug Skills: Proficiency in debugging low-level firmware and kernel-level issues using Verdi, SimVision, and hardware-software co-debug tools
• Education: BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience: 8+ years in ASIC Emulation or Verification, with significant experience on large-scale Palladium installations
• Technical Skills: Mastery of SystemVerilog, Verilog, and C/C++ for transactor development and reference modeling.
• Protocol Knowledge: Deep understanding of data center protocols including PCIe, DDR and AMBA AXI/NoC

Responsibilities

• Massive-Scale Model Architecture: Lead the partitioning and compilation of our design across a multi-rack Palladium environment, optimizing for performance and debug visibility.
• Software Enablement (Left-Shift): Create and maintain the hybrid emulation and co-simulation environments (using SCE-MI or DPI) that allow our software teams to boot OS images and run AI workloads on pre-silicon hardware.
• Full-Stack Validation: Design and execute comprehensive emulation test plans to verify high-speed interfaces (PCIe Gen 6/7, 112G+VSR, Ethernet) and complex AI memory hierarchies.
• Performance & Power Analysis: Utilize Palladium’s Dynamic Power Analysis (DPA) and throughput monitors to identify "true peaks" and performance bottlenecks that simulation cannot capture.
• Vendor Management: Act as the primary technical point of contact with Cadence R&D to troubleshoot tool issues and leverage the latest Palladium Z3 capabilities.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level