SoC Design Verification Engineer

Altera•San Jose, CA

16h

About The Position

Altera is one of the world's leading providers of programmable solutions. With a renewed focus on agility, software-first, and AI-driven solutions, Altera is shaping the future of computing by providing flexible technology, empowering innovators with scalable products, from high-performance to power- and cost-optimized devices for cloud, network, and edge applications. Join us in our journey to becoming the #1 FPGA provider in the world as we redefine the next era of programmable innovations! About the Team & About the Role The HPS Design Verification Team is responsible for validating the processor subsystem of Altera FPGA products. As a SoC Design Verification Engineer you will have the opportunity to; Perform functional logic verification of an integrated SoC to ensure design will meet specifications. Define and develop scalable and re-usable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Execute verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicate, root causes, and debugs issues in the pre-silicon environment. Find and implement corrective measures to resolve failing tests. Collaborate and communicate with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Document test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporate and execute security activities within test plans, including regression and debug tests, to ensure security coverage. Maintain and improve existing functional verification infrastructure and methodology. Absorb learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Salary Range Our compensation reflects the cost of labor within the US market. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $128.9k - $205.9k USD

Requirements

7+ years of work experience in logical hardware design and verification.
Must be fully knowledgeable of programming in SystemVerilog and UVM hardware descriptive languages.
Must possess a background of unit or block ownership in a full hardware design life cycle.
Bachelor’s degree in electrical engineering, computer engineering, computer science or similarly related fields.

Nice To Haves

10+ years of work experience in logical hardware design and verification.
A strong background in Design for Debug verification is strongly needed. Specifically, experience with ARM Coresight debugger verification will be valuable.
Objected oriented programming in languages like C++, Java.
Scripting in languages like Python, Perl and Tcl is desired.
A background in using AI techniques in design and verification is very much desired.

Responsibilities

Perform functional logic verification of an integrated SoC to ensure design will meet specifications.
Define and develop scalable and re-usable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
Execute verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
Replicate, root causes, and debugs issues in the pre-silicon environment.
Find and implement corrective measures to resolve failing tests.
Collaborate and communicate with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Document test plans and drives technical reviews of plans and proofs with design and architecture teams.
Incorporate and execute security activities within test plans, including regression and debug tests, to ensure security coverage.
Maintain and improve existing functional verification infrastructure and methodology.
Absorb learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products.