SLD FPGA Verification Engineer III - Lunar Permanence

Blue Origin•Space Coast, WA

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! This role is part of the Lunar Permanence business unit, which develops Blue Origin’s Blue Moon landers and related products. To further Blue Origin's mission of millions of people living and working in space for the benefit of Earth, we are building sustainable infrastructure for our transport of crew and cargo from Earth to the lunar surface. As part of a hardworking team, you will participate in verification of FPGA-based solutions within Sustaining Lunar Development program’s avionics, guidance, and navigation group. This includes requirements development with design engineers, verification through formal methods, UVM based simulation and on-target testing. Our FPGA team is tightly knit and very collaborative, with a variety of experience and backgrounds. We care about the success of each other and our peers and are very willing to help each other learn and grow. Together we will build high-reliability, safety-critical avionics solutions for our Human Landing System (HLS) vehicle. As such, experience with DO-254 is a plus. We are looking for someone to apply their technical expertise, leadership skills, and dedication to quality to positively impact safe human spaceflight. Passion for our mission and vision is required!

Requirements

BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study
5+ years experience verifying FPGAs or ASICSs
In-depth experience using RTL simulation tools such as Siemens QuestaSim, ModelSim, or equivalent
In-depth knowledge of System Verilog and the Universal Verification Methodology (UVM).
Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from scratch.
Understands different types of coverage, usage of cover classes, cover points, etc.
Experience with predictive testbench components, functional coverage and assertions.
Experience with constrained random verification.
Experience with the Register Abstraction Layer.

Nice To Haves

Familiarity with the following are also helpful AXI protocols, PCIe, Ethernet, SPI, I2C interfaces
Debugging FPGA/ASIC hardware and assisting with HW/SW integration.
Managing regression and continuous integration infrastructure within GITLab
Knowledge of scripting languages such as Python, Perl, or TCL/Shell for automation.
Working knowledge of NPR 7150.2, DO-254, or other safety-critical software standard.

Responsibilities

Perform requirements-based verification of FPGAs using Universal Verification Methodology (UVM).
Create comprehensive verification and validation plan that encompasses functional and system level verification and validation.
Develop IP/subsystem/system level testbench and tests to achieve required coverage goals.
Document plans and procedures.
Write directed and random test cases.
Generate reports in support of certification of the design to a high DAL.
Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
Reviewing verification and validation results against the coverage goals.
Writing, analyzing and achieving coverage metrics.
Experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required.

Benefits

Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion.
Bonus amounts and eligibility are not guaranteed and subject to change and cancellation.

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