Silicon Packaging Design Engineer

Intel Corporation•Chandler, AZ

1d•Onsite

About The Position

As a Silicon Packaging Design Engineer, you will play a critical role in the development of advanced substrate designs that drive Intel's innovation and technological leadership. This position offers a unique opportunity to contribute to cutting-edge technologies by managing the end-to-end development process of substrate designs, from concept to tapeout. You will collaborate with silicon and hardware teams to optimize design performance, cost efficiency, and manufacturability, ensuring Intel remains at the forefront of high-performance applications. Your contributions will directly impact Intel's ability to deliver world-class solutions that address global challenges in computing. Join Intel and contribute to shaping the future of technology. Be a part of a dynamic team committed to delivering innovative solutions that address the needs of a rapidly evolving world. Apply today to take the next step in your career.

Requirements

US Citizenship
Bachelor's degree in Electrical Engineering, Mechanical Engineering, or Material Sciences, with 0-1+ years of relevant experience, or related field.
Experience with package design tools such as Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
Experience with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversions.
Experience microelectronic package or PCB physical layout design and manufacturing processes.
Strong analytical ability and problem-solving skills, including debugging and providing innovative solutions.

Nice To Haves

Master Degree in Electrical Engineering, Mechanical Engineering, or Material Sciences or related field.
Experience in substrate design or I/O routing, or technology development.
Experience with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS.
Experience with scripting using Python, VB, C, or similar languages.

Responsibilities

Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
Conduct substrate fit and routing studies to establish design, performance, and cost tradeoffs.
Define and implement substrate design rules, conducting internal and external reviews to maintain quality standards.
Analyze data, resolve Design Rule Checks (DRCs), and optimize designs for manufacturability and performance.
Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.
Complete documentation and collateral into the product lifecycle management system of record.