Senior Verification Engineer
About The Position
SEAKR is currently seeking a Verification Engineer who is responsible for developing verification and simulation strategies, conducting design reviews, creating a digital test plan and providing coverage metrics. The Engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test. The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements. Ability to architect and construct full test environments for complex devices using UVM, including coverage, is required. The candidate shall be capable of diagnosing sophisticated test failures and filing results, and be capable of analyzing code coverage to adjust agent sequence behavior. Ability to provide direction to less senior verification engineers is required. Ability to lead a team of verification engineers to fully verify a device is required. Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required. Ability to analyze Verilog RTL to diagnose test failures is required. Ability to analyze VHDL is a plus. Must be able to work effectively under pressure to meet tight deadlines. Experience verifying Ethernet and PCIe designs a plus. Experience using/integrating verification IP into existing environments a plus Experience verifying DSP related designs a plus.
Requirements
- A Bachelors degree in Electrical Engineering or Computer Science
- A minimum of 10 years of verification engineering experience are required
- Ability to analyze Verilog RTL to diagnose test failures is required
- Ability to architect and construct full test environments for complex devices using UVM, including coverage, is required
- Ability to lead a team of verification engineers to fully verify a device is required
- Ability to provide direction to less senior verification engineers is required
- Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required
- Must be able to work effectively under pressure to meet tight deadlines
- The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements
- The Engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test
Nice To Haves
- A Master's Degree is preferred
- Ability to analyze VHDL is a plus
- Experience verifying Ethernet and PCIe designs a plus
- Experience using/integrating verification IP into existing environments a plus
- Experience verifying DSP related designs a plus
Responsibilities
- Developing verification and simulation strategies
- Conducting design reviews
- Creating a digital test plan and providing coverage metrics
- Construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology)
- Performing and evaluating regression tests for a design under test
- Extracting and deriving test requirements and sequences for an interface or interfaces based on available design documentation and requirements
- Architecting and constructing full test environments for complex devices using UVM, including coverage
- Diagnosing sophisticated test failures and filing results
- Analyzing code coverage to adjust agent sequence behavior
- Providing direction to less senior verification engineers
- Leading a team of verification engineers to fully verify a device
- Using simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting
- Analyzing Verilog RTL to diagnose test failures
Benefits
- SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan.
- In addition to base salary, employees are eligible for a year-end bonus.
- SEAKR offers a variety of paid leave, such as vacation, sick, bereavement, and FMLA.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
501-1,000 employees
