Senior Design Verification Engineer

Altera Semiconductor • San Jose, CA

1d

About The Position

About Altera Altera is at the forefront of enabling the future of advanced semiconductor solutions. We specialize in delivering world-class programmable logic devices, embedded systems, and high-performance accelerators that power cutting-edge applications across telecommunications, data centers, aerospace, and emerging AI workloads. Our culture thrives on innovation, collaboration, and excellence — empowering talented engineers to design breakthrough technologies that shape tomorrow.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
• 10+ years of professional Design Verification experience in ASIC/FPGA environments.
• 7+ years of hands-on experience with SystemVerilog for testbench and verification development.
• 5+ years of experience using UVM (Universal Verification Methodology) in production verification environments.
• 5+ years of experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
• 3+ years of experience with coverage-driven verification and functional coverage closure.
• Experience with industry-standard scripting languages such as Python, Perl, or TCL (3+ years).
• Ability to debug complex RTL/design issues using simulation and waveform analysis (5+ years).
• Strong written and verbal communication skills, with experience documenting verification plans and results (5+ years).

Nice To Haves

• Advanced degree (Master’s or Ph.D.) in Electrical/Computer Engineering or equivalent.
• Experience with formal verification tools (e.g., JasperGold, OneSpin).
• Experience with hardware emulation/prototyping platforms.
• Familiarity with Version Control Systems (e.g., Git) and CI/CD flows for verification automation.
• Prior mentorship or team leadership experience.
• Knowledge of high-speed interfaces (e.g., PCIe, Ethernet, DDR) verification.
• Exposure to Python-based verification frameworks and automation flows.

Responsibilities

• Lead the development and execution of comprehensive verification plans for complex digital ASIC/FPGA designs.
• Define and implement robust verification strategies using industry-standard methodologies (e.g., UVM, SystemVerilog).
• Build high-quality, reusable verification IP and testbench environments.
• Analyze functional coverage and testbench metrics to drive closure and quality.
• Debug design and verification issues alongside architects, RTL designers, and implementation teams.
• Mentor and guide junior verification engineers and contribute to best practices across the team.
• Collaborate with cross-functional partners to accelerate verification throughput and support product release goals.
• Drive continuous improvement of verification flows and automation.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior