Senior UCIe PHY Expert, MLA Technology

Amazon • Austin, TX

12d

About The Position

Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

In Annapurna Labs we are at the forefront of hardware/software co-design not just in Amazon Web Services (AWS) but across the industry. Our Machine Learning Accelerator (MLA) Technology is seeking a UCIe PHY expert who is interested in diving deep into the definition, design, validation, and data center operation of AWS’s next generation machine learning silicon and servers.

As a senior member of our technology team, you will have opportunities to participate in the design and execution of UCIe, SERDES, and general high speed analog technologies, with the goal of creating the most stable machine learning platforms within AWS’s data centers. A senior UCIE engineer on our team needs to be able to work with vendors and internal design teams, understand UCIe timings and features, write/modify tests at scale, debug fleet wide issues, and collect data from manufacturing and the data center.

Our broader team has end to end ownership of some of the most complicated IPs on the most advanced server hardware in the world. We drive complex technical debug efforts involving our IPs and leverage the massive scale of EC2 to monitor, optimize, and improve our machine learning hardware reliability on behalf of our customers.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Systems Engineering, or related fields
• 7+ years of experience in Silicon development
• 3+ years in SOC/IO/Subsystems Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area
• Good understanding of UCIe at the PHY and controller level
• Good knowledge of UCIe training, timing parameters and/or controller features
• Support the physical design team with IP integration, 2.5D packaging, clocking and timing constraints
• Ability to create scripts (lua, bash, python, etc.) to accomplish functional day to day tasks.
• Drive cross-functional triage effort on functional and performance issues
• Take the leadership role in post-silicon bring-up of UCIe-Advanced or Standard
• Perform system-level debug and root-cause analysis through bring-up, characterization, validation and production phases

Nice To Haves

• MS degree in computer science, electrical engineering, or related field
• Strong Firmware development skills within embedded environments
• Good leadership skills and ability to multi-task and thrive in a dynamic environment
• Knowledge of UCIe phy and controller related protocols
• Good communication skills and interpersonal skills

Responsibilities

• Collaborate with architects, design teams, and software engineers on our next generation ML chips
• Support on-going debug and operations of previous ML chips within manufacturing and the data center
• Dive deep into IP integration, packaging, silicon bring up, characterization, and validation of our UCIe subsystems
• Independently develop the scripts you need to execute and collaborate with software engineers as your needs scale

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Senior