PHY Design Verification Engineer

Apple • San Diego, CA

2d

About The Position

Would you like to join Apple’s growing wireless silicon development team? Our
wireless SoC organization is responsible for all aspects of wireless silicon
development with a particular emphasis on highly energy-efficient design and new
technologies that transform the user experience at the product level, all of
which is driven by a world-class vertically integrated engineering team spanning
RF/Analog architecture and design, Systems/PHY/MAC architecture and design,
VLSI/RTL design and integration, Design Verification, Emulation, Test and
Validation, and FW/SW engineering.

In this highly visible role, you will be at the center of a silicon design group
with a critical impact on delivering world-class silicon to empower wireless
products for hundreds of millions of customers. As a PHY Design Verification
Engineer, you will be responsible for pre-silicon RTL verification of wireless
PHY and its interfaces with the rest of the wireless communication SoC. You will
interact with DV methodologists, designers, and communication systems engineers
to develop reusable testbench and verification environment deploying the latest
methodology with metric-driven verification, ensuring the highest design
quality.

Requirements

• Minimum requirements of bachelor's degree.

Nice To Haves

• Verification experience of wireless/wired communication block/subsystem.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
• Experience of using Matlab/C reference model and bit-accurate verification.
• Verification experience of wireless/wired communication block/subsystem.
• Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
• Proficient in shell and Python scripting, Perl scripting. Experience of using AI technologies in data mining/analysis. Experience of Palladium/FPGA validation.
• Should be a team player with excellent communication skills, self-motivated and well organized.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees